Intuition The one core ideaA flip-flop is a tiny box that remembers one bit and only changes its mind at the exact flick of a clock. Everything below — logic gates, feedback loops, high/low signals, "edges" — exists to build and explain that one sentence.
Before you can trust the parent note's line "Q n + 1 = D own about a dozen little ideas. The parent quietly assumed them. This page builds each one from nothing, in an order where every new idea only leans on ideas already introduced.
Definition Binary signal (logic level)A wire in a digital circuit is, at any moment, at one of exactly two voltage levels . We give them names:
high = logic 1 low = logic 0
Forget voltages for now. Picture a light switch: it is either ON or OFF , never halfway. A digital wire is that switch. When we draw a signal over time , we draw a line that sits either "up high" (1) or "down low" (0) and jumps between them.
Why the topic needs it: the whole flip-flop stores one bit — one of these two values. Its input D C L K Q 1 0
A logic gate is a small circuit that reads one or more input levels and produces one output level, following a fixed rule. The two the parent uses:
NOT (inverter): output is the opposite of the input.NOR : output is 1 only when all inputs are 0 0
Definition Notation for the rules
The bar X NOT X — flip it. (0 = 1 1 = 0
The plus A + B OR — it is 1 A or B 1
The dot A ⋅ B AND — it is 1 A and B 1
So A + B
Common mistake The plus is NOT ordinary additionFeels right: + 1 + 1 2 Wrong: in logic, + 1 + 1 = 1 0 1 Fix: read + or ", and ⋅ and ", every single time.
Why the topic needs it: the flip-flop is built entirely out of NOR (and later AND/NOT) gates. The parent writes Q = R + Q
R + Q R = 0 , Q = 1
Q = 1 = 0 R + Q = 0 + 0 = 0 0 = 1 1 executed a NOR gate by hand.
A truth table lists every combination of input levels and the output for each. With n 2 n cannot miss a case.
A B A + B A ⋅ B A + B
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
1
1
1
1
0
table and not a formula-in-words
A gate has only a handful of possible inputs, so the honest, complete way to define its behaviour is to show all of them. The parent's characteristic table for the flip-flop (D , Q n → Q n + 1
Why the topic needs it: every claim like "S = R = 0 ⇒
Feedback means an output wire is routed back to become one of the inputs. The circuit's output now depends partly on its own previous output.
Intuition The picture: a loop that can "hold"Picture two people, each shouting the opposite of what the other says. Once they settle on a pair like "A says UP / B says DOWN", nobody has a reason to change — the loop is stable and remembers that arrangement. That self-sustaining loop is memory. No loop, no memory; a plain gate forgets its input the instant the input goes away.
A circuit with two stable states it can rest in (here Q = 0 Q = 1
Why the topic needs it: the SR latch — the beating heart of the flip-flop — is exactly two NOR gates wired in a feedback loop. The parent's line "Memory is just a stable loop" is this idea. Without feedback there is no storage, and the entire chapter collapses.
Definition State subscriptsBecause the output loops back (feedback), we must talk about "now" versus "after the next clock tick":
Q n current stored value ("present state", the value before this edge).Q n + 1 right after the next active edge ("next state").
Intuition The picture: a filmstripThink of time chopped into frames by the clock. Q n Q n + 1
Why the topic needs it: the parent's central equation Q n + 1 = D Q n + 1 after the edge". Miss the subscript and you'll think the output changes continuously — it doesn't.
C L K clock is a special wire whose value marches 0 , 1 , 0 , 1 , 0 , 1 , … when to act.
Definition Level vs. edge
A level is a stretch of time where the clock sits high (or sits low).
An edge is the brief transition between levels:
rising / positive edge ↑ = the moment 0 → 1 falling / negative edge ↓ = the moment 1 → 0
duration , edge = an instant
Level-triggered = "acts during the whole time the clock is high" (a wide window). Edge-triggered = "acts only at the knife-thin instant of the jump" (a snapshot). The parent's whole reason to exist is preferring the edge — the snapshot — because it happens once and closes fast.
Why the topic needs it: "edge-triggered D flip-flop" is a clock idea. Positive-edge, active edge, keep-out window — all of it needs you to distinguish level from edge first.
Common mistake "The clock powers the circuit"Feels right: it's always running, like a battery.
Wrong: the clock is a timing signal , a metronome — it says when , not how much energy . Power comes from the supply rails.
Fix: hear the clock as a drummer counting the band in, not the amplifier.
Definition Propagation delayGates are not instant. When an input changes, the output changes a tiny time later . That lag is the propagation delay. Chaining gates adds up their delays.
On a waveform, whenever an input jumps, the dependent output jumps slightly to the right (later in time). Those small right-shifts, summed along a path, are why the parent's timing budget t c q + t co mb + t s u addition : three delays happening one after another.
Why the topic needs it: setup time, hold time, clock-to-Q, and f ma x when signals become valid. Time-on-the-x-axis and "changes cost delay" are the prerequisites for the whole timing section.
Binary signal 0 or 1 on a wire
Edge triggered D flip-flop
Read it bottom-up: bits on wires → gates → (tables + feedback) → bistable memory → add a clock and its edges + the notion of present/next state + timing → the parent topic.
Test yourself; each line hides its answer.
What are the only two values a digital wire can hold? Logic 1 0
In logic, what does the bar X Flips the bit: 0 = 1 1 = 0
In logic, what does + 1 + 1 + OR ; 1 + 1 = 1
In logic, what does ⋅ AND — output is 1 1
State the NOR rule in words. Output is 1 all inputs are 0 0
Why does a truth table capture every case? With n 2 n
What does feedback (a looped-back output) make possible? Memory — a stable loop that holds its last value (a bistable).
What do Q n Q n + 1 Q n Q n + 1
Difference between a clock level and a clock edge ? A level is a stretch of time sitting high or low; an edge is the instant of transition (0 → 1 1 → 0
What is a rising (positive) edge? The moment the clock goes 0 → 1
Why is f ma x The delays (t c q t co mb t s u
