Edge-triggered D flip-flop: Question bank — Hardware deep dive

For notation: $D$ is the data input, $C L K$ the clock, $Q$ the stored output, $\overline{Q}$ its complement, and $Q_{n + 1}$ the state after the active edge. A rising edge ↑ is the clock going $0 \to 1$ .

True or false — justify

A D flip-flop copies

D

Q

the whole time the clock is high.

False — that describes a transparent Gated D latch; the flip-flop samples

D

only at the instant of the edge and then locks, ignoring

D

while the clock stays high.

The characteristic equation

Q_{n + 1} = D

means the next state ignores the current state

Q_{n}

True — the D flip-flop simply loads

D

; unlike the JK flip-flop, its next state has no

Q_{n}

term, so history before the edge doesn't matter.

A master–slave D flip-flop has both latches open at the same moment.

False — they run on opposite enables, so exactly one is transparent at any time; that non-overlap is precisely what turns level behaviour into edge behaviour (Master-slave configuration).

D

is held constant forever,

Q

eventually equals

D

True — at the first active edge after

D

settles,

Q

takes

D

and then every later edge just re-loads the same value, so

Q

stays equal to

D

Violating hold time can only corrupt data if you also violate setup time.

False — setup and hold are independent windows; changing

D

just after the edge (a hold violation) can push the flip-flop into Metastability even if setup was perfectly satisfied.

Connecting

\overline{Q}

back to

D

makes the output toggle every edge.

True — since

D = \overline{Q_{n}}

, each edge loads the opposite of the current output, giving

Q_{n + 1} = \overline{Q_{n}}

, a divide-by-2 like a T flip-flop.

A single SR latch is already edge-triggered.

False — the SR latch responds continuously to its inputs (level behaviour); you need two gated latches with opposite enables to get an edge.

Two D flip-flops on the same clock, with stage 1's

Q

feeding stage 2's

D

, will shift data one stage per edge.

True — because each flip-flop closes its input almost instantly at the edge, stage 2 captures the old output of stage 1, not the new one; this is the basis of Registers and shift registers.

Increasing the clock frequency indefinitely is safe as long as the flip-flops are fast.

False — the period must satisfy

T_{c l k} \geq t_{c q} + t_{co mb} + t_{s u}

; once

T_{c l k}

shrinks below that, the receiving flip-flop samples data that hasn't settled (Setup and hold time).

A negative-edge flip-flop samples

D

when the clock is low.

False — it samples at the falling transition

1 \to 0

; being low afterward is irrelevant, just as being high is irrelevant for a positive-edge device.

Spot the error

"The forbidden state

S = R = 1

can still occur in a gated D latch if

D

glitches."

Error — in the Gated D latch,

S = D \cdot E

and

R = \overline{D} \cdot E

are complementary when enabled, so

S = R = 1

is structurally impossible regardless of

D

's value.

"Clock-to-Q delay

t_{c q}

is the time

D

must be stable before the edge."

Error — that's the setup time

t_{s u}

;

t_{c q}

is the delay from the edge to a valid

Q

, measured after the edge, not before it.

"In the divide-by-2 circuit, the output frequency equals the input clock frequency."

Error — since

Q

flips once per edge, it takes two edges to complete one output cycle, so the output frequency is half the clock frequency.

"To be safe,

f_{ma x} = 1/ (t_{c q} \cdot t_{co mb} \cdot t_{s u})

Error — the delays occur in series along one data path, so they add, not multiply:

f_{ma x} = 1/ (t_{c q} + t_{co mb} + t_{s u})

"During the clock-high level, changing

D

updates

Q

because the clock is still active."

Error — the flip-flop already captured

D

at the edge and locked; the high level is not the trigger, so mid-level changes are ignored (the "camera shutter" fires only at the edge).

"Metastability is a permanent stuck state that never resolves."

Error — it is a temporary unstable balance that resolves to a valid 0 or 1 after an unpredictable delay; the danger is that this delay can occasionally exceed the time budget.

"A latch is preferred over a flip-flop for shift registers because it's transparent."

Error — transparency is exactly the problem: with transparent latches, data races through all stages in one clock phase; edge-triggering is required for a clean one-hop-per-tick shift.

Why questions

Why does the master latch in a master–slave FF freeze just before the value seen at the edge, rather than during the clock-high phase?

Because the master is enabled by

\overline{C L K}

; when

C L K

rises the master's enable falls, so it captures whatever

D

was at that transition and then ignores all later changes.

Why does edge-triggering give the whole computer a "global heartbeat"?

Because every flip-flop samples at the same edge and then holds, so all state updates happen together, exactly once per tick, removing races between stages (Clock distribution and skew then handles making that edge arrive on time).

Why can't we build reliable feedback loops (like counters) out of transparent latches alone?

Because a transparent latch would let the new output feed back and change its own input within the same clock phase, causing uncontrolled oscillation; the edge closes the loop's input so each state advances exactly once per clock (Synchronous counters).

Why is the setup-and-hold "keep-out window" straddled around the edge rather than only before it?

The internal latch needs

D

stable both approaching the sampling instant (setup) and while it locks in just after (hold); a change on either side can catch the latch mid-transition and cause Metastability.

Why does the D flip-flop's next state not depend on

Q_{n}

, unlike JK?

Because its input logic directly forces

S = D

R = \overline{D}

at the edge, overwriting the stored bit entirely; the JK flip-flop instead has a "hold" and "toggle" mode that reads

Q_{n}

back into the equation.

Edge cases

What happens to

Q

if no clock edge ever arrives after power-up?

Q

stays at whatever bistable state the feedback loop settled into — possibly random — because with no edge there is no sampling event to load a defined value.

D

changes exactly at the active edge (inside the keep-out window), what is

Q_{n + 1}

Undefined — this violates setup/hold and can drive the flip-flop metastable, so it may resolve to 0, to 1, or hover before settling after an unpredictable delay.

For a positive-edge FF, what does a falling edge

1 \to 0

do to

Q

Nothing — it is not the active edge, so

Q

is frozen and

D

is completely ignored during and after that transition.

t_{co mb} = 0

(a flip-flop's

Q

wired straight into the next flip-flop's

D

), what limits the clock?

The period must still satisfy

T_{c l k} \geq t_{c q} + t_{s u}

, and you must also check that

t_{c q}

exceeds the hold time so the new value doesn't arrive before the receiver has locked in the old one.

At the very first edge after

\overline{Q}

is wired to

D

(toggle setup) with

Q

starting at 0, what is

Q

after the edge?

Q

becomes 1, because

D = \overline{Q} = 1

was present at the edge and gets loaded, and it will alternate

1, 0, 1, \dots

on every subsequent edge.

Recall The single test that catches most traps

Ask "when exactly can $Q$ change?" — the honest answer is always "only during the active clock edge, to the value $D$ had just before it." Every trap on this page is a disguised way of forgetting that one sentence.

Connections

Parent: Edge-triggered D flip-flop
SR latch, Gated D latch, Master-slave configuration — the build layers
JK flip-flop, T flip-flop — richer next-state logic
Setup and hold time, Metastability — timing correctness
Registers and shift registers, Synchronous counters — where the traps bite in practice
Clock distribution and skew — delivering that shared edge