3.4.4Sequential Circuits

JK and T flip-flops

2,032 words9 min readdifficulty · medium3 backlinks

WHY do we need JK at all?

WHAT is wrong? When S=R=1S=R=1, we ask the circuit to make Q=1Q=1 AND Q=0Q=0 simultaneously. In a real gate this produces a race and an unpredictable output. That single wasted row is a design sin.

HOW does JK fix it? JK renames SJS\to J, RKR\to K, and reroutes the J=K=1J=K=1 case to mean "toggle" (Qnext=QQ_{next}=\overline{Q}). Nothing else changes.


Deriving the JK from first principles

Build JK from SR by making the internal set/reset depend on the current state: S=JQ,R=KQS = J\cdot \overline{Q}, \qquad R = K\cdot Q

Why this step? S=JQS=J\overline Q means "only try to set when we are currently 00" (Q=1\overline Q=1). R=KQR=KQ means "only try to reset when we are currently 11". Because QQ and Q\overline Q can never both be 1, the internal SS and RR can never both be 1 — the forbidden combination is now structurally impossible. That is the whole magic.

Now plug into the SR characteristic equation. First derive SR's: Qnext=S+RQQ_{next} = S + \overline{R}\,Q

Why? S=1S=1 forces Qnext=1Q_{next}=1. Otherwise (S=0S=0) we keep QQ unless R=1R=1 resets it — hence RQ\overline R Q.

Substitute S=JQS=J\overline Q, R=KQR=KQ: Qnext=JQ+(KQ)QQ_{next} = J\overline Q + \overline{(KQ)}\,Q

Simplify KQQ=(K+Q)Q=KQ+QQ=KQ+0=KQ\overline{KQ}\cdot Q = (\overline K + \overline Q)Q = \overline K Q + \overline Q Q = \overline K Q + 0 = \overline K Q.

Why this step? KQ=K+Q\overline{KQ}=\overline K+\overline Q (De Morgan), and QQ=0\overline Q Q=0. So:

Check the four rows against the boxed formula to convince yourself — that is the point of deriving it.


The T flip-flop = JK with J=K=TJ=K=T

Derive its characteristic equation by putting J=K=TJ=K=T into the JK equation: Qnext=TQ+TQQ_{next} = T\overline Q + \overline T Q

Why this step? That expression is exactly the definition of XOR.

WHY it matters: a chain of T flip-flops (each fed the previous one's output) is a ripple counter — each stage toggles at half the rate of the one before, giving frequency division by 2, 4, 8, …

Figure — JK and T flip-flops

Excitation tables (for designing circuits)

Characteristic tables answer "given inputs, what's the output?". Excitation tables answer the reverse — "I want this transition, what inputs do I need?" — which is what you actually use when building counters.

Why the don't-cares in JK? To go 010\to1 we need to set, so J=1J=1; but KK is irrelevant because KK only acts when Q=1Q=1. That freedom (X) is what makes JK cheaper to implement in K-maps.


Worked examples


Common mistakes


Flashcards

JK characteristic equation
Qnext=JQ+KQQ_{next} = J\overline{Q} + \overline{K}Q
What does J=K=1J=K=1 do in a JK flip-flop?
Toggle: Qnext=QQ_{next}=\overline Q
How is the SR forbidden state eliminated in JK?
Internally S=JQ, R=KQS=J\overline Q,\ R=KQ, so SS and RR can never both be 1
T flip-flop characteristic equation
Qnext=TQQ_{next} = T \oplus Q
What does T=0T=0 do?
Hold (keep current QQ); toggling only happens when T=1T=1
Relation between T and JK
T is a JK with J=K=TJ=K=T tied together
Excitation for transition 010\to1 in JK
J=1, K=XJ=1,\ K=X
Excitation for transition 101\to0 in JK
J=X, K=1J=X,\ K=1
Excitation input for T given Q,QnextQ,Q_{next}
T=QQnextT = Q \oplus Q_{next} (1 iff state must change)
Why does a T flip-flop divide clock frequency by 2?
With T=1T=1 it toggles every edge, so output completes one cycle per two clock cycles
SR characteristic equation
Qnext=S+RQQ_{next} = S + \overline{R}Q (with SR=0SR=0)
Recall Feynman: explain to a 12-year-old

Imagine a light switch. A basic SR switch has two buttons: one says "ON", one says "OFF". If you press both at once it gets confused and no one knows what happens. The JK switch is smarter: pressing both buttons together now means "flip me — if I'm on, turn off; if I'm off, turn on." The T switch is even simpler: it has just one button, and every time you press it (T=1) the light flips. Press it again, it flips back. If you tap that button steadily, the light blinks half as fast as your taps — that's how computers count!

Connections

  • SR Flip-Flop — the parent JK is derived from
  • D Flip-Flop — the other "no forbidden state" fix (Qnext=DQ_{next}=D)
  • Edge-Triggering and Master-Slave — why JK doesn't race
  • Ripple Counters — built from cascaded T flip-flops
  • Excitation Tables and Sequential Design
  • Karnaugh Maps — where JK's don't-cares reduce logic
  • XOR Gate — the heart of the T flip-flop

Concept Map

has flaw

fixed by

uses

makes S=JQ' R=KQ

char eq

substitute

reroutes forbidden to

tie J=K=T

char eq

specialised as

SR flip-flop

S=R=1 forbidden

JK flip-flop

Feed back current Q

Qnext = S + R'Q

Qnext = JQ' + K'Q

J=K=1 toggles

T flip-flop

Qnext toggles on T=1

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, kahani simple hai. Pehle SR flip-flop hota hai — do input, Set aur Reset. Problem ye ki jab dono ek saath 1 ho jaate hain (S=R=1S=R=1), circuit confuse ho jaata hai, output undefined. Ye ek "forbidden" state hai jo waste hoti hai. JK flip-flop isi problem ka smart solution hai: usi forbidden combination ko ek naya, useful kaam de diya — toggle (matlab output ulta ho jaata hai). Trick ye hai ki andar se S=JQS=J\overline Q aur R=KQR=KQ bana dete hain, isliye SS aur RR kabhi dono 1 ho hi nahi sakte. Isse characteristic equation banti hai Qnext=JQ+KQQ_{next}=J\overline Q+\overline K Q.

T flip-flop to aur simple hai — JK ke dono input jodkar ek single wire TT bana do. Agar T=1T=1 to har clock edge pe output flip, agar T=0T=0 to hold. Iski equation Qnext=TQQ_{next}=T\oplus Q hai, yaani XOR. Yaad rakho: XOR ka matlab "T aur Q alag honge to output 1", isliye toggle hota hai.

Ye kyun important hai? Kyunki T flip-flop se counters bante hain. Ek T flip-flop T=1T=1 pe har edge toggle karta hai, to output clock se aadhi speed pe chalta hai — frequency ÷2. Aise kai flip-flop jodkar binary counter ban jaata hai jo computer mein counting aur timing ke liye use hota hai.

Exam tip: characteristic table (input se output) aur excitation table (desired transition se required input) ko mat mixup karna. Counter design karte waqt excitation table use hoti hai — JK ke don't-care (X) K-map simplify karne mein help karte hain.

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections