Exercises — JK and T flip-flops

$J=1,K=0$ is the set row. Plug into the equation: $Q_{next}=J\overline{Q}+\overline{K}Q=(1)(\overline{0})+(\overline{0})(0)=1\cdot 1+1\cdot 0=1.$ Answer: $Q_{next}=1$. WHAT we did: substituted the given inputs and $Q=0$. WHY: the equation is the table, so it must agree — and it says "set".

$Q_{next}=T\oplus Q=0\oplus 1=1.$ $\oplus$ gives 1 only when the inputs disagree; $0$ and $1$ disagree, so the result is $1$. Answer: $Q_{next}=1$ (hold). $T=0$ always holds — it never changes the stored bit.

$J=1,K=1$. Toggle means $Q_{next}=\overline{Q}$: whatever is stored, flip it. Check: $J\overline{Q}+\overline{K}Q=1\cdot \overline{Q}+0\cdot Q=\overline{Q}$. ✓

Use $Q_{next}=J\overline{Q}+\overline{K}Q$ step by step.

• Edge 1 ($Q=0$, set): $1\cdot 1+1\cdot 0=1$. → $Q=1$.
• Edge 2 ($Q=1$, toggle): $1\cdot 0+0\cdot 1=0$. → $Q=0$.
• Edge 3 ($Q=0$, reset): $0\cdot 1+0\cdot 0=0$. → $Q=0$. Sequence of $Q$: $1,0,0$.

$T=1$ ⇒ toggle every edge: $Q$ after edges $\mathrm{1..6}$ is $1,0,1,0,1,0.$ WHAT this looks like: the output completes ONE full cycle (0→1→0) every two clock edges (see figure). So $f_{out}=f_{clk}/2$ — a ÷2 divider. This is the building block of a ripple counter.

To move from 1 to 0 we must reset, so $K=1$. And $J$? $J$ only ever acts when $Q=0$ (it multiplies $\overline{Q}$); we're at $Q=1$, so $J$ is irrelevant → $J=X$ (don't care). Answer: $J=X,K=1$.

The excitation table:

Read the transitions in order:

• $0\to 1$: $J=1,K=X$
• $1\to 1$: $J=X,K=0$
• $1\to 0$: $J=X,K=1$
• $0\to 0$: $J=0,K=X$

WHY don't-cares appear: e.g. in $1\to 1$ we just must not reset, so $K=0$; $J$ is idle at $Q=1$, hence $X$.

Compute $S\cdot R=(J\overline{Q})(KQ)=JK(\overline{Q}Q)$. But $\overline{Q}Q=0$ always (a bit and its complement can't both be 1). So $S\cdot R=JK\cdot 0=0.$ $S\cdot R=0$ means $S$ and $R$ are never simultaneously 1, for any $J,K,Q$. The SR forbidden row is therefore structurally impossible — not hidden, genuinely eliminated. (See SR Flip-Flop.)

• T: $T=Q\oplus Q_{next}=0\oplus 0=0$. Forced, no freedom.
• JK: $0\to 0$ needs $J=0,K=X$ — a don't-care on $K$. WHY it matters: don't-cares are free choices a K-map can fill with whatever minimises the logic, so JK-based designs often need fewer gates. T has no don't-cares (its input is fully determined by $Q\oplus Q_{next}$).

List states and required transitions, then $T=Q\oplus Q_{next}$ per bit:

• $T_0$ is 1 in every row → $T_0=1$ (LSB toggles every clock).
• $T_1=1$ exactly when $Q_0=1$ → $T_1=Q_0$ (MSB toggles when LSB is 1).

Design: $T_0=1,T_1=Q_0$. This is a ripple counter — feed $Q_0$ to clock/enable the next stage. Each bit toggles at half the rate of the one below (÷2 per stage), matching L2.2.

Wire $J=D$ and $K=\overline{D}$. Substitute into the JK equation: $Q_{next}=J\overline{Q}+\overline{K}Q=D\overline{Q}+\overline{\overline{D}}Q=D\overline{Q}+DQ=D(\overline{Q}+Q)=D\cdot 1=D.$ So $Q_{next}=D$ regardless of $Q$ — exactly a D flip-flop. WHY it works: setting $K=\overline{D}$ makes "reset" active precisely when $D=0$, and "set" active when $D=1$, so the stored bit always follows $D$.

Substitute into $Q_{next}=J\overline{Q}+\overline{K}Q$ with $J=\overline{Q},K=Q$: $Q_{next}=\overline{Q}\cdot \overline{Q}+\overline{Q}\cdot Q=\overline{Q}+0=\overline{Q}.$ So $Q_{next}=\overline{Q}$ always — this wiring is a permanent toggler, identical to a T flip-flop with $T=1$. From $Q=0$: $0,1,0,1,\dots$ — a ÷2 divider. (Compare L2.2: same waveform, different construction.)

Desired: $Q_{next}=1$ when $S=1$, else $Q_{next}=Q$. So the target is $Q_{next}=S+Q$ (set-dominant hold). Then $T=Q\oplus Q_{next}=Q\oplus (S+Q).$ Evaluate the cases:

• $S=1$: $Q_{next}=1$, so $T=Q\oplus 1=\overline{Q}$ → toggles from 0 to 1 (sets), and if already 1 gives $T=0$ (harmless hold — matching the controller assumption).
• $S=0$: $Q_{next}=Q$, so $T=Q\oplus Q=0$ → hold. Answer: $T=Q\oplus (S+Q)$, which simplifies to $T=S\overline{Q}$ (set only when currently 0). Verify: $S\overline{Q}=1$ only when $S=1,Q=0$ — precisely the one edge where a toggle is needed to reach 1.

Each stage divides by 2, so after $n$ stages $f_{out}=16/2^n$ MHz. Set $16/2^n=1\Rightarrow 2^n=16\Rightarrow n=4$. Answer: 4 stages give $1\text{ MHz}$. (Check per stage: 8, 4, 2, 1 MHz.)