JK and T flip-flops: Worked examples — Hardware deep dive

#	Case class	What makes it its own case	Killed by
A	JK — all 4 input rows, one edge	$J, K \in {0, 1}$ each behave differently: hold / reset / set / toggle	Ex 1
B	JK toggle from both start states	Toggle depends on current $Q$ ; $Q = 0$ and $Q = 1$ give opposite results	Ex 2
C	JK — degenerate "hold" (inputs 00)	Nothing changes; the boring-but-vital no-op	Ex 3
D	T flip-flop — the $T = 0$ trap	People assume T "always toggles"; $T = 0$ holds	Ex 4
E	T flip-flop — limiting behaviour ( $T = 1$ forever)	Frequency division; needs many edges, not one	Ex 5
F	Design (reverse): given a transition, find JK inputs	Uses the excitation table + don't-cares	Ex 6
G	Design (reverse): find T input for a transition	$T = Q \oplus Q_{n e x t}$	Ex 7
H	Real-world word problem	Translate "count seconds" into flip-flop stages	Ex 8
I	Exam twist — $J, K$ change every clock, trace a waveform	Combine A+B over a timeline; watch for edge-only update	Ex 9
J	Exam twist — the race / level-triggered gotcha	Why the equation needs [[Edge-Triggering and Master-Slave	edge-triggering]]

Worked examples

Worked example Ex 1 — (Cell A) All four JK rows in one shot

Start at $Q = 0$ . On four separate clock edges (each starting again from $Q = 0$ ) apply $(J, K) = (0, 0), (0, 1), (1, 0), (1, 1)$ . Give $Q_{n e x t}$ for each.

Forecast: guess the four outputs before reading — which one flips you?

$(0, 0)$ : $Q_{n e x t} = J \overline{Q} + \overline{K} Q = 0 \cdot 1 + 1 \cdot 0 = 0$ . → hold. Why this step? Plug into the boxed characteristic equation; with $Q = 0$ we have $\overline{Q} = 1, Q = 0$ .
$(0, 1)$ : $Q_{n e x t} = 0 \cdot 1 + \overline{1} \cdot 0 = 0 + 0 = 0$ . → reset (already 0, stays 0). Why this step? $K = 1$ enables reset, but $Q$ is already 0, so no visible change.
$(1, 0)$ : $Q_{n e x t} = 1 \cdot 1 + 1 \cdot 0 = 1$ . → set. Why this step? $J = 1$ with $\overline{Q} = 1$ drives the set term to 1.
$(1, 1)$ : $Q_{n e x t} = 1 \cdot 1 + \overline{1} \cdot 0 = 1$ . → toggle (from 0 to 1). Why this step? Both high = toggle; toggling 0 gives 1.

Verify: table read directly off the parent's characteristic table for $Q = 0$ : hold→0, reset→0, set→1, toggle→1. ✓ Match.

Worked example Ex 8 — (Cell H) Word problem: a 3-bit second-counter

A digital clock needs a stage that counts $0, 1, 2, \dots, 7$ then wraps, driven by a $1 Hz$ tick. Using T flip-flops with $T = 1$ on the least-significant stage, how many stages are needed, and what frequency comes out of the most-significant stage?

Forecast: how many flip-flops for 8 values, and how slow is the top bit?

To count 8 distinct values you need $n$ bits with $2^{n} \geq 8$ , so $n = 3$ stages. Why this step? $n$ bits represent $2^{n}$ states; $2^{3} = 8$ exactly.
Each T stage (with $T = 1$ , fed by the previous stage) halves the frequency: stage outputs run at $1/2, 1/4, 1/8$ of the tick. Why this step? Cell E showed one T stage divides by 2; cascading multiplies the division — this is a ripple counter.
Most-significant (3rd) stage frequency $= \frac{1 Hz}{2 ^{3}} = \frac{1}{8} = 0.125 Hz$ . Why this step? Three divide-by-2 stages give $2 \times 2 \times 2 = 8$ total division.

Verify: $2^{3} = 8 \geq 8$ ✓; $1/8 = 0.125$ Hz ✓ (one full cycle of the top bit every 8 seconds — matches a mod-8 counter wrapping every 8 ticks).

Worked example Ex 9 — (Cell I) Exam twist: JK waveform with changing inputs

A JK flip-flop starts at $Q = 0$ . Over 4 clock edges the inputs are, edge by edge: $(J, K) = (1, 0), (1, 1), (0, 0), (0, 1)$ . Trace $Q$ after each edge.

Forecast: four different rows in a row — track the state carefully, it feeds forward.

Edge 1, $(1, 0)$ , $Q = 0$ : set → $Q_{n e x t} = 1 \cdot 1 + 1 \cdot 0 = 1$ . Now $Q = 1$ . Why this step? $J = 1$ sets; state becomes 1 and carries into the next edge.
Edge 2, $(1, 1)$ , $Q = 1$ : toggle → $Q_{n e x t} = 1 \cdot 0 + 0 \cdot 1 = 0$ . Now $Q = 0$ . Why this step? Both high toggles from 1 to 0 (Cell B logic).
Edge 3, $(0, 0)$ , $Q = 0$ : hold → $Q_{n e x t} = 0 + 1 \cdot 0 = 0$ . Now $Q = 0$ . Why this step? $J = K = 0$ freezes the state (Cell C).
Edge 4, $(0, 1)$ , $Q = 0$ : reset → $Q_{n e x t} = 0 + 0 \cdot 0 = 0$ . Stays $Q = 0$ . Why this step? $K = 1$ resets, but already 0, so no change.

Full trace: $Q = 0 \to 1 \to 0 \to 0 \to 0$ .

Verify: each output equals $J \overline{Q} + \overline{K} Q$ evaluated at the current $Q$ : $1, 0, 0, 0$ ✓ — and note the state at each edge feeds the next, which is the whole point of a sequential circuit.

Worked example Ex 10 — (Cell J) Exam twist: the race / level-triggered gotcha

A transparent (level-triggered, not edge-triggered) JK sees $J = K = 1$ held for the entire clock-high phase, which lasts long enough for the gates to settle $6$ times. Starting $Q = 0$ , what does the naive characteristic equation say, and what really happens?

Forecast: does it toggle once, or spin?

Naive equation (one update assumption): $Q_{n e x t} = \overline{Q}$ , so $0 \to 1$ , a single toggle. Why this step? The characteristic equation assumes exactly one update per edge.
Reality with 6 settle-throughs: the output feeds back while $J = K = 1$ still holds, so it toggles again and again: $0 \to 1 \to 0 \to 1 \to 0 \to 1 \to 0$ . Why this step? A transparent latch re-evaluates continuously; toggle-then-feed-back is an oscillator.
After an even 6 toggles from 0: $Q = 0$ — but the value at the end is unpredictable in practice because it depends on exact gate delays, not a clean count. Why this step? This is the race the parent warned about; the cure is edge-triggering / master–slave, which permits one toggle per edge.

Verify: parity check — 6 toggles (even) returns to start: $0 \to 0$ ✓; the lesson is that the equation is only valid under one update per edge, which real hardware must enforce.

Coverage check

Recall Did we hit every cell of the matrix?

Cell A (all 4 JK rows) ::: Ex 1 Cell B (toggle from both start states) ::: Ex 2 Cell C (degenerate hold) ::: Ex 3 Cell D ( $T = 0$ holds, not toggles) ::: Ex 4 Cell E (limiting $T = 1$ forever ⇒ ÷2) ::: Ex 5 Cell F (reverse JK design, don't-cares) ::: Ex 6 Cell G (reverse T design, $T = Q \oplus Q_{n e x t}$ ) ::: Ex 7 Cell H (real-world 3-bit counter) ::: Ex 8 Cell I (waveform, changing inputs) ::: Ex 9 Cell J (race / level-triggered gotcha) ::: Ex 10

Connections

Parent: JK and T flip-flops — the machinery these examples exercise
SR Flip-Flop — the ancestor whose forbidden state we now trace safely
D Flip-Flop — compare the "no forbidden state" behaviour
Edge-Triggering and Master-Slave — resolves Ex 10's race
Ripple Counters — Ex 5 and Ex 8 are single stages of one
Excitation Tables and Sequential Design — powers Ex 6 and Ex 7
Karnaugh Maps — where Ex 6's don't-cares pay off
XOR Gate — the engine inside every T example

Worked examples — JK and T flip-flops

The scenario matrix

Worked examples

Coverage check

Connections