JK and T flip-flops: Question bank — Hardware deep dive

Every symbol used here is defined in the parent note. Quick anchor so line one makes sense:

Recall Symbol reminder

$Q$ = the flip-flop's current stored bit. $Q_{n e x t}$ = the bit after the next clock edge. $\overline{Q}$ = "not $Q$ " (the opposite bit). $\oplus$ = XOR ("output 1 when the two inputs disagree"). $J, K$ = the two JK inputs; $T$ = the single toggle input; $S, R$ = set/reset of the older SR Flip-Flop.

True or false — justify

A JK flip-flop still has one forbidden input combination, just like SR.

False. SR breaks at

S = R = 1

, but JK routes

J = K = 1

to a defined action — toggle. Internally

S = J \overline{Q}, R = K Q

, so

S

and

R

can never both be 1, killing the hazard structurally.

A T flip-flop toggles its output on every clock edge.

False. It toggles only when

T = 1

. When

T = 0

it holds. The characteristic is

Q_{n e x t} = T \oplus Q

, not

Q_{n e x t} = \overline{Q}

Setting

J = 0, K = 0

makes a JK flip-flop output 0.

False.

J = K = 0

is the hold command:

Q_{n e x t} = Q

, so it keeps whatever it already had (could be 1). To force 0 you need the reset row

J = 0, K = 1

Q_{n e x t} = T \oplus Q

and

Q_{n e x t} = T \overline{Q} + \overline{T} Q

describe the same flip-flop.

True. XOR is the sum-of-products "the two inputs disagree", so

T \oplus Q = T \overline{Q} + \overline{T} Q

by definition. See XOR Gate.

A T flip-flop can be built from a JK flip-flop but not the other way around.

True in the simple sense. Tying

J = K = T

gives T. Going backward, a lone T input can't recreate the four independent JK commands (it collapses set and reset into one toggle line), so you lose set/reset control.

Excitation tables and characteristic tables contain the same information in different layouts.

Mostly true, but the direction differs. Characteristic: inputs → output. Excitation: desired transition → required inputs. The excitation table also introduces don't-cares (X) that the characteristic table never shows.

The don't-care

K = X

for the JK transition

0 \to 1

means

K

is broken or floating.

False. It means

K

's value is irrelevant here: when

Q = 0

K

(which only acts to reset an already-1 output) has no effect. Either

K = 0

K = 1

produces

0 \to 1

, so you're free to pick whichever simplifies the logic.

A level-triggered (transparent) JK with

J = K = 1

held high behaves identically to an edge-triggered one.

False. A transparent JK toggles repeatedly while the clock is high (the "race" problem). Edge-triggered / master–slave designs toggle exactly once per edge — see Edge-Triggering and Master-Slave.

The D Flip-Flop and the JK flip-flop both eliminate the forbidden state, so they are interchangeable.

False in purpose. Both avoid a forbidden state, but D just copies its input (

Q_{n e x t} = D

) with no hold/toggle, while JK gives independent hold/set/reset/toggle. They solve the same problem differently.

Cascading T flip-flops (each fed the previous output) divides the clock frequency by 2 at each stage.

True. Each stage with

T = 1

toggles once per input edge, so its output cycles at half its input's rate — giving ÷2, ÷4, ÷8… This is exactly a ripple counter.

Spot the error

J = K = 1

sets the output to 1 because both inputs are high."

Error: high-high is toggle, not set.

Q_{n e x t} = \overline{Q}

, so the result depends on the current state — it could go to 0.

"To hold the output, use

J = 1, K = 1

so both agree to keep it."

Error:

J = K = 1

toggles. Hold is

J = K = 0

. The mnemonic is "J sets, K kills, both flip."

"For the JK transition

1 \to 1

we need

J = 1, K = 1

Error: the excitation row

1 \to 1

J = X, K = 0

. We only require "don't reset" (

K = 0

);

J

is a don't-care because setting is pointless when already at 1.

T = Q_{n e x t}

tells you the toggle input from a desired next state."

Error: the correct excitation is

T = Q \oplus Q_{n e x t}

— you need

T = 1

exactly when the state must change, which depends on both current and next state, not

Q_{n e x t}

alone.

"Since T means Toggle, a T flip-flop with

T = 0

holds the inverted value."

Error:

T = 0

holds the value as-is (

Q_{n e x t} = Q

), no inversion. Inversion happens only for

T = 1

"SR's characteristic equation is

Q_{n e x t} = S + R Q

Error: it's

Q_{n e x t} = S + \overline{R} Q

(with the constraint

S R = 0

). We keep

Q

only when

R

is not asserted, hence

\overline{R}

, not

R

"In JK we substitute

S = J Q

and

R = K \overline{Q}

to feed back the state."

Error: it's the other way:

S = J \overline{Q}

(set only when currently 0) and

R = K Q

(reset only when currently 1). Swapping them would break the toggle behaviour.

Why questions

Why does feeding

Q

back into the inputs eliminate the forbidden state?

Because

S = J \overline{Q}

and

R = K Q

depend on complementary signals

\overline{Q}

and

Q

— one is always 0 — so internal

S

and

R

can never be 1 simultaneously. The illegal input becomes physically unreachable.

Why does XOR appear in the T flip-flop equation and not, say, AND or OR?

Because "toggle when

T = 1

, hold when

T = 0

" is precisely "output differs from

Q

exactly when

T = 1

" — the disagreement rule, which is the definition of XOR.

Why are the don't-cares in the JK excitation table valuable for design?

Each X is a free choice a K-map can set to whatever simplifies the Boolean expression, producing cheaper, smaller logic than a fully-specified table would allow.

Why does a T flip-flop, not a D flip-flop, naturally build a binary counter?

A counter bit must flip each time its stage should advance; T's toggle-on-command does this directly by wiring

T = 1

, whereas D would need external feedback (

D = \overline{Q}

) to imitate the same toggle.

Why does the JK characteristic equation assume exactly one update per clock edge?

Because the equation gives one

Q_{n e x t}

per current

Q

. A transparent JK held with

J = K = 1

would keep re-toggling, contradicting the single-valued equation — hence real designs enforce one update per edge.

Why is

J = K = 1

called "useful" rather than "illegal", unlike

S = R = 1

Because it produces a fully defined, repeatable output (

\overline{Q}

) that we deliberately use for counting and dividing frequency — a feature, not a fault.

Edge cases

What does a JK flip-flop do if

J = K = 1

is applied but the clock never ticks?

Nothing — a clocked/edge-triggered flip-flop only updates on the active clock edge. With no edge,

Q

stays put regardless of the inputs.

A T flip-flop starts at an unknown

Q

and gets

T = 1

for one edge. What is

Q_{n e x t}

The opposite of whatever it started as. Toggle inverts the current bit, so an unknown start gives an unknown-but-inverted result — you still don't know the absolute value without knowing the start.

For the JK transition

0 \to 0

, both

J

and

K

have constraints — true?

False. The excitation is

J = 0, K = X

: we must not set (

J = 0

), but

K

is a don't-care since resetting an already-0 output changes nothing.

If you build a T flip-flop from JK but accidentally tie only

J = T

and leave

K = 0

, what happens?

It becomes a set-only / hold device, never a toggler:

J = 1

sets to 1 and stays, since

K = 0

can never reset. You lose the toggle entirely.

What is

Q_{n e x t}

for a JK flip-flop with

J = 0, K = 1

when

Q

is already 0?

Still 0. This is the reset row; resetting an already-0 output is a no-op, so

Q_{n e x t} = 0

In a ripple counter of T flip-flops, why doesn't every stage update at the same instant?

Each stage's clock is driven by the previous stage's output transition, so toggles ripple through with small delays — the source of the "ripple" name and of timing skew in ripple counters.

Connections

Parent: JK and T flip-flops
SR Flip-Flop — the forbidden-state ancestor
D Flip-Flop — the other no-forbidden-state design
Edge-Triggering and Master-Slave — why held toggling doesn't race
Ripple Counters — cascaded T flip-flops
Excitation Tables and Sequential Design — the design-direction tables
Karnaugh Maps — where don't-cares pay off
XOR Gate — the heart of the T equation