SR latch operation

WHY does a latch exist?

The Set–Reset latch is the simplest such loop with two control inputs:

S (Set) → force output $Q=1$ .
R (Reset) → force output $Q=0$ .

WHAT is the structure? (NOR version)

Wiring (NOR version): $Q = \overline{R + \overline{Q}} \qquad \overline{Q} = \overline{S + Q}$

Read this as: " $Q$ is the NOR of $R$ and the other output; $\overline{Q}$ is the NOR of $S$ and $Q$ ."

HOW does it behave? — deriving the truth table from scratch

We derive each row using the NOR rule: NOR output is 1 only if BOTH inputs are 0.

Case 1: Hold ( $S=0, R=0$ )

Suppose currently $Q=1,\ \overline{Q}=0$ .

$Q = \overline{R+\overline{Q}} = \overline{0+0} = \overline{0} = 1$ ✓ (stays 1)
$\overline{Q} = \overline{S+Q} = \overline{0+1} = \overline{1} = 0$ ✓ (stays 0)

Why this step? Both equations reproduce the values we assumed → the state is self-consistent = stable. It equally holds $Q=0$ . So $S=R=0$ ⇒ keep previous value (this is the memory).

Case 2: Set ( $S=1, R=0$ )

$\overline{Q} = \overline{S+Q} = \overline{1+\text{anything}} = \overline{1} = 0$ .
Then $Q = \overline{R+\overline{Q}} = \overline{0+0} = 1$ .

Why this step? A 1 on any NOR input forces that gate's output to 0. So $S=1$ forces $\overline{Q}=0$ , which then releases the other gate to output $Q=1$ . Result: == $Q=1$ == (Set).

Case 3: Reset ( $S=0, R=1$ )

$Q = \overline{R+\overline{Q}} = \overline{1+\dots} = 0$ .
Then $\overline{Q} = \overline{S+Q} = \overline{0+0} = 1$ .

Why this step? Symmetric to Set: $R=1$ forces $Q=0$ . Result: == $Q=0$ == (Reset).

Case 4: Forbidden ( $S=1, R=1$ )

$Q = \overline{1+\dots} = 0$ and $\overline{Q} = \overline{1+\dots} = 0$ .

Why this step? Both outputs become 0 simultaneously, so $Q$ and $\overline{Q}$ are no longer complementary — the naming is violated. Worse: if $S$ and $R$ then drop to $0$ at the same instant, both gates try to go high, and the final state depends on tiny timing/gate-delay differences → unpredictable / metastable. Hence forbidden / invalid.

Deriving the characteristic equation

We want $Q_{next}$ as a function of $S,R,Q_{prev}$ for the three legal rows:

$S=1,R=0 \Rightarrow Q_{next}=1$
$S=0,R=1 \Rightarrow Q_{next}=0$
$S=0,R=0 \Rightarrow Q_{next}=Q_{prev}$

"Force to 1 when Set; keep old value if not being Reset" gives $Q_{next} = S + \overline{R}\,Q_{prev}, \quad \text{with constraint } SR=0.$ The constraint $SR=0$ is just the promise never to press Set and Reset together.

The NAND version (active-LOW $\overline{S},\overline{R}$ )

NAND rule: output is 0 only if BOTH inputs are 1 (i.e. output is 1 if any input is 0).

\begin{array}{cc|c} \overline{S} & \overline{R} & Q_{next}\\\hline 1 & 1 & Q_{prev}\ (\text{Hold})\\ 0 & 1 & 1\ (\text{Set})\\ 1 & 0 & 0\ (\text{Reset})\\ 0 & 0 & \text{invalid (both }=1)\\ \end{array}

Why inverted? NAND with a 0 input is forced high, so 0 is the active value. Everything is the logical dual of the NOR latch — same behavior, roles of 0 and 1 swapped on the inputs.

Worked example: tracing a timing sequence (NOR latch)

Inputs over time (each step, $S$ then $R$ ), starting unknown, we power up and drive:

step	S	R	action	Q
0	0	1	Reset	0
1	0	0	Hold	0
2	1	0	Set	1
3	0	0	Hold	1
4	0	1	Reset	0

Why step 1? After Reset, $Q=0$ . With $S=R=0$ , the Hold rule reproduces $0$ → so $Q$ stays 0 even though no input is active. That "sticking" is exactly the memory. Why step 3? After Set, $Q=1$ ; Hold keeps it at $1$ . The latch remembered the Set that happened one step earlier — proof it stores a bit.

Common mistake Steel-manning the common errors

Mistake 1: "For a NAND latch, $\overline{S}=1,\overline{R}=1$ should be forbidden, since 1,1 was forbidden for NOR." Why it feels right: You memorized "11 = forbidden" as a rule. The fix: The forbidden combo is always the one that forces both outputs equal. For NOR that's $S=R=1$ ; for NAND it's $\overline{S}=\overline{R}=0$ . NAND's $11$ is actually Hold. Reason from gate behavior, not from the pattern of bits.

Mistake 2: " $S=R=0$ makes $Q=0$ (both zero → output zero)." Why it feels right: Zeros look like "off," so output must be off. The fix: $S=R=0$ means "do nothing," so the output is whatever it was — could be 0 or 1. It's Hold, not clear.

Mistake 3: " $Q$ and $\overline{Q}$ are just labels; they're always opposite." Why it feels right: They're named as complements. The fix: In the forbidden state they are both 0 (NOR) — genuinely not complementary. The complement guarantee only holds for the three legal inputs.

Recall Feynman: explain it to a 12-year-old

Imagine two kids holding a rope, each one leaning back to keep the other standing. That balance can lean left (call it 1) or right (call it 0), and once it's leaning it stays leaning by itself — that's remembering. The S button shoves it to lean left (1). The R button shoves it to lean right (0). If you press nothing, it keeps leaning the way it already was. If you push both buttons at once, both kids fall over and nobody knows who gets up first — that's the "forbidden" move you're not allowed to make.

Active recall

An SR latch is built from which cross-coupled gates (two variants)?

Two cross-coupled NOR gates (active-HIGH) OR two cross-coupled NAND gates (active-LOW).

Why can a latch store a bit while a plain gate cannot?

The outputs feed back into the inputs (a loop), so a stable state re-asserts itself even after inputs are removed — combinational gates have no feedback.

NOR SR latch: what does S=0, R=0 do?

Hold — Q keeps its previous value (this is the memory state).

NOR SR latch: what does S=1, R=0 do?

Set — Q = 1.

NOR SR latch: what does S=0, R=1 do?

Reset — Q = 0.

NOR SR latch: why is S=1, R=1 forbidden?

Both Q and Q̄ become 0 (not complementary), and if both inputs drop to 0 together the final state is unpredictable/metastable.

State the characteristic equation of an SR latch.

Q_next = S + (R̄)·Q_prev, valid under the constraint S·R = 0.

For a NAND (active-LOW) SR latch, which input combination is Hold?

S̄=1, R̄=1 (both inputs HIGH) → Hold.

For a NAND SR latch, which combination is forbidden?

S̄=0, R̄=0 (both inputs LOW) → forces both outputs to 1, invalid.

In the NOR latch, what does a logic 1 on any NOR input do?

Forces that gate's output to 0 (NOR outputs 1 only when both inputs are 0).

What is metastability in an SR latch?

An unstable in-between state after leaving the forbidden condition, where the output settles unpredictably depending on gate delays.

Connections

Cross-coupled gates — the general feedback trick behind all latches.
Gated SR latch — adds an enable so inputs only matter when the gate is high.
D latch — removes the forbidden state by tying $R=\overline{S}$ .
JK flip-flop — fixes SR's forbidden $1,1$ by making it toggle.
Flip-flop vs latch — level-triggered (latch) vs edge-triggered (flip-flop).
Metastability — the deeper reason $S=R=1$ is dangerous.
NOR gate / NAND gate — the primitive building blocks.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, SR latch ka basic funda ye hai ki hum do gates (NOR ya NAND) ko aise cross-connect karte hain ki har gate ka output doosre gate ke input me jaata hai. Is feedback loop ki wajah se circuit apni state khud hold kar leta hai — matlab ek bit ki memory ban jaati hai. Normal gate to sirf present input pe depend karta hai (combinational), par yahan output khud input ban ke apni value ko baar-baar reinforce karta rehta hai. Isiliye ye smallest memory element hai.

NOR version me inputs active-HIGH hote hain: S=1 karo to $Q=1$ (Set), R=1 karo to $Q=0$ (Reset). Sabse important cheez — jab S=0 aur R=0, tab kuch nahi badalta, purani value hold rehti hai. Yahi memory wala magic hai. Ek common galti ye hoti hai ki log sochte hain "dono 0 matlab output 0" — nahi bhai, dono 0 matlab "do nothing", jo pehle tha wahi rahega.

Forbidden state ( $S=R=1$ ) me dono outputs 0 ho jaate hain, jo galat hai kyunki $Q$ aur $\overline{Q}$ opposite hone chahiye. Aur agar tum dono inputs ek saath 0 kar do, to gate delays ke hisaab se koi bhi state aa sakti hai — isko metastability kehte hain, bilkul unpredictable. Isiliye is combination ko avoid karna hai.

NAND version bas ulta hai: wahan inputs active-LOW hote hain, yaani 0 action karta hai. To NAND me $\overline{S}=\overline{R}=1$ Hold hai aur $\overline{S}=\overline{R}=0$ forbidden. Rule ratne se acha hai gate ka behaviour samajh lo: forbidden wahi hai jahan dono outputs equal ho jaate hain. Isse aage chal ke D latch aur JK flip-flop banenge jo is forbidden problem ko solve karte hain.

WHY does a latch exist?

WHAT is the structure? (NOR version)

HOW does it behave? — deriving the truth table from scratch

Case 1: Hold ( $S=0, R=0$ )

Case 2: Set ( $S=1, R=0$ )

Case 3: Reset ( $S=0, R=1$ )

Case 4: Forbidden ( $S=1, R=1$ )

Deriving the characteristic equation

The NAND version (active-LOW $\overline{S},\overline{R}$ )

Worked example: tracing a timing sequence (NOR latch)

Active recall

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections