SR latch operation — Hinglish notes

3.4.1 · Hardware › Sequential Circuits

WHY ek latch exist karta hai?

Set–Reset latch do control inputs ke saath sabse simple aisa loop hai:

S (Set) → output $Q = 1$ force karo.
R (Reset) → output $Q = 0$ force karo.

WHAT hai structure? (NOR version)

Wiring (NOR version): $Q = \overline{R + \overline{Q}} \overline{Q} = \overline{S + Q}$

Ise aise padho: " $Q$ , $R$ aur dusre output ka NOR hai; $\overline{Q}$ , $S$ aur $Q$ ka NOR hai."

HOW behave karta hai? — truth table scratch se derive karna

Hum har row NOR rule se derive karte hain: NOR output 1 tabhi hota hai jab DONO inputs 0 hon.

Case 1: Hold ( $S = 0, R = 0$ )

Maano abhi $Q = 1, \overline{Q} = 0$ hai.

$Q = \overline{R + \overline{Q}} = \overline{0 + 0} = \overline{0} = 1$ ✓ (1 rehta hai)
$\overline{Q} = \overline{S + Q} = \overline{0 + 1} = \overline{1} = 0$ ✓ (0 rehta hai)

Yeh step kyun? Dono equations wahi values reproduce karti hain jo humne assume ki thi → state self-consistent hai = stable. Yeh $Q = 0$ ke liye bhi utna hi valid hai. Toh $S = R = 0$ ⇒ keep previous value (yeh hai memory).

Case 2: Set ( $S = 1, R = 0$ )

$\overline{Q} = \overline{S + Q} = \overline{1 + anything} = \overline{1} = 0$ .
Phir $Q = \overline{R + \overline{Q}} = \overline{0 + 0} = 1$ .

Yeh step kyun? Kisi bhi NOR input par 1 us gate ke output ko 0 force karta hai. Toh $S = 1$ , $\overline{Q} = 0$ force karta hai, jo phir dusre gate ko $Q = 1$ output karne deta hai. Result: == $Q = 1$ == (Set).

Case 3: Reset ( $S = 0, R = 1$ )

$Q = \overline{R + \overline{Q}} = \overline{1 + \dots} = 0$ .
Phir $\overline{Q} = \overline{S + Q} = \overline{0 + 0} = 1$ .

Yeh step kyun? Set ke symmetric: $R = 1$ , $Q = 0$ force karta hai. Result: == $Q = 0$ == (Reset).

Case 4: Forbidden ( $S = 1, R = 1$ )

$Q = \overline{1 + \dots} = 0$ aur $\overline{Q} = \overline{1 + \dots} = 0$ .

Yeh step kyun? Dono outputs ek saath 0 ban jaate hain, toh $Q$ aur $\overline{Q}$ ab complementary nahi hain — naming violate ho gayi. Isse bhi bura: agar $S$ aur $R$ phir ek hi waqt $0$ par drop kar jaayein, toh dono gates high jaane ki koshish karte hain, aur final state chhoti timing/gate-delay differences par depend karti hai → unpredictable / metastable. Isliye forbidden / invalid.

Characteristic equation derive karna

Hum $Q_{n e x t}$ ko $S, R, Q_{p r e v}$ ke function ke roop mein teen legal rows ke liye chahte hain:

$S = 1, R = 0 \Rightarrow Q_{n e x t} = 1$
$S = 0, R = 1 \Rightarrow Q_{n e x t} = 0$
$S = 0, R = 0 \Rightarrow Q_{n e x t} = Q_{p r e v}$

"Set hone par 1 force karo; purani value rakho agar Reset nahi ho raha" se milta hai: $Q_{n e x t} = S + \overline{R} Q_{p r e v}, with constraint S R = 0.$ Constraint $S R = 0$ sirf woh promise hai ki Set aur Reset ek saath press nahi karoge.

NAND version (active-LOW $\overline{S}, \overline{R}$ )

NAND rule: output 0 tabhi hota hai jab DONO inputs 1 hon (matlab output 1 hota hai agar koi bhi input 0 ho).

\overline{S} 1010 \overline{R} 1100 Q_{n e x t} Q_{p r e v} (Hold) 1 (Set) 0 (Reset) invalid (both = 1)

Inverted kyun? NAND ke saath 0 input high force hota hai, toh 0 active value hai. Sab kuch NOR latch ka logical dual hai — same behavior, inputs par 0 aur 1 ke roles swap hain.

Worked example: timing sequence trace karna (NOR latch)

Time ke saath inputs (har step mein, $S$ phir $R$ ), unknown se start karke, power up karte hain aur drive karte hain:

step	S	R	action	Q
0	0	1	Reset	0
1	0	0	Hold	0
2	1	0	Set	1
3	0	0	Hold	1
4	0	1	Reset	0

Step 1 kyun? Reset ke baad, $Q = 0$ . $S = R = 0$ ke saath, Hold rule $0$ reproduce karta hai → toh $Q$ 0 rehta hai bhaale koi input active na ho. Woh "sticking" bilkul wahi memory hai. Step 3 kyun? Set ke baad, $Q = 1$ ; Hold use $1$ par rakhta hai. Latch ne us Set ko yaad rakkha jo ek step pehle hua tha — proof hai ki woh ek bit store karta hai.

Common mistake Common errors ko steel-man karna

Galti 1: "NAND latch ke liye, $\overline{S} = 1, \overline{R} = 1$ forbidden hona chahiye, kyunki NOR ke liye 1,1 forbidden tha." Kyun sahi lagta hai: Tumne "11 = forbidden" ek rule ki tarah memorize kar liya. The fix: Forbidden combo hamesha woh hoti hai jo dono outputs equal force kare. NOR ke liye woh $S = R = 1$ hai; NAND ke liye $\overline{S} = \overline{R} = 0$ . NAND ka $11$ actually Hold hai. Bits ke pattern se nahi, gate behavior se reason karo.

Galti 2: " $S = R = 0$ , $Q = 0$ banata hai (dono zero → output zero)." Kyun sahi lagta hai: Zeros "off" lagte hain, toh output off hona chahiye. The fix: $S = R = 0$ ka matlab hai "kuch mat karo," toh output wahi hai jo tha — 0 ya 1 ho sakta hai. Yeh Hold hai, clear nahi.

Galti 3: " $Q$ aur $\overline{Q}$ sirf labels hain; yeh hamesha opposite hain." Kyun sahi lagta hai: Unhe complements ke roop mein name kiya gaya hai. The fix: Forbidden state mein yeh dono 0 hote hain (NOR) — genuinely complementary nahi. Complement guarantee sirf teen legal inputs ke liye hold karti hai.

Recall Feynman: 12 saal ke bacche ko samjhao

Socho do bacche ek rope pakde hain, har ek doosre ko khada rakhne ke liye peechhe jhuk raha hai. Woh balance left jhuk sakta hai (use 1 kaho) ya right (use 0 kaho), aur ek baar jhukne ke baad woh khud-ba-khud jhuka rehta hai — yeh yaad rakhna hai. S button use left jhukne ke liye dhakka deta hai (1). R button use right jhukne ke liye dhakka deta hai (0). Agar tum kuch nahi dabate, woh waisi hi side jhuka rehta hai jaise pehle tha. Agar tum dono buttons ek saath dabate ho, dono bacche gir jaate hain aur koi nahi jaanta pehle kaun uthega — yeh woh "forbidden" move hai jo tumhe karna hi nahi chahiye.

Active recall

An SR latch is built from which cross-coupled gates (two variants)?

Do cross-coupled NOR gates (active-HIGH) YA do cross-coupled NAND gates (active-LOW).

Why can a latch store a bit while a plain gate cannot?

Outputs inputs mein feed back hote hain (ek loop), toh ek stable state khud ko re-assert karta rehta hai inputs remove hone ke baad bhi — combinational gates mein koi feedback nahi hota.

NOR SR latch: what does S=0, R=0 do?

Hold — Q apni previous value rakhta hai (yeh memory state hai).

NOR SR latch: what does S=1, R=0 do?

Set — Q = 1.

NOR SR latch: what does S=0, R=1 do?

Reset — Q = 0.

NOR SR latch: why is S=1, R=1 forbidden?

Q aur Q̄ dono 0 ban jaate hain (complementary nahi), aur agar dono inputs ek saath 0 par drop karein toh final state unpredictable/metastable hoti hai.

State the characteristic equation of an SR latch.

Q_next = S + (R̄)·Q_prev, valid constraint S·R = 0 ke under.

For a NAND (active-LOW) SR latch, which input combination is Hold?

S̄=1, R̄=1 (dono inputs HIGH) → Hold.

For a NAND SR latch, which combination is forbidden?

S̄=0, R̄=0 (dono inputs LOW) → dono outputs ko 1 force karta hai, invalid.

In the NOR latch, what does a logic 1 on any NOR input do?

Us gate ke output ko 0 force karta hai (NOR tabhi 1 output karta hai jab dono inputs 0 hon).

What is metastability in an SR latch?

Forbidden condition chhodne ke baad ek unstable in-between state, jahan output unpredictably settle hoti hai gate delays par depend karte hue.

Connections

Cross-coupled gates — woh general feedback trick jo saare latches ke peeche hai.
Gated SR latch — ek enable add karta hai taaki inputs tabhi matter karein jab gate high ho.
D latch — forbidden state hataata hai $R = \overline{S}$ tie karke.
JK flip-flop — SR ke forbidden $1, 1$ ko fix karta hai use toggle banaakar.
Flip-flop vs latch — level-triggered (latch) vs edge-triggered (flip-flop).
Metastability — deeper reason kyun $S = R = 1$ dangerous hai.
NOR gate / NAND gate — primitive building blocks.