D latch and gated latches

1. WHY do we need this? (from the SR latch problem)

WHY is this bad? Two problems:

The forbidden state $S=R=1$ makes $Q$ and $\overline{Q}$ both equal — a contradiction — and the final state is a race condition.
The latch reacts to inputs immediately and at all times. In a real circuit signals arrive at slightly different moments ("glitches"), and the latch would flip randomly.

We solve #2 with a gate/enable, and #1 with the D trick.

2. The Gated SR Latch — adding a control wire

HOW it's built: take an SR latch, and feed it $S' = S\cdot E$ and $R' = R\cdot E$ .

$Q_{\text{next}} = \begin{cases} \text{hold} & E=0 \\[2pt] \text{SR behaviour}(S,R) & E=1 \end{cases}$

$E$	$S$	$R$	$Q_{\text{next}}$
0	x	x	$Q$ (hold)
1	0	0	$Q$ (hold)
1	1	0	1 (set)
1	0	1	0 (reset)
1	1	1	forbidden

Progress! We now control when. But the forbidden state still exists. Enter the D latch.

3. The D Latch — killing the forbidden state

Deriving the next-state equation from first principles:

Starting from the gated SR latch with $S=D$ , $R=\overline D$ :

If $E=1$ $E = 1$ : $S'=D,\ R'=\overline D$ $S^{'} = D, R^{'} = \overline{D}$ .
- $D=1 \Rightarrow S'=1,R'=0 \Rightarrow Q=1$
- $D=0 \Rightarrow S'=0,R'=1 \Rightarrow Q=0$
- So $Q_{\text{next}} = D$ .
If $E=0$ : $S'=R'=0 \Rightarrow$ hold, so $Q_{\text{next}} = Q$ .

Combining both cases into ONE boolean expression:

$\boxed{Q_{\text{next}} = E\cdot D + \overline{E}\cdot Q}$

4. Worked examples

Worked example Example 1 — Tracking outputs over time

Enable and data sequences (each column = one time step):

t	1	2	3	4	5
E	1	1	0	0	1
D	0	1	0	1	1
Q	?	?	?	?	?

Start with $Q=0$ .

t1: $E=1$ → $Q=D=0$ . Why? Enable open, output copies data.
t2: $E=1$ → $Q=D=1$ . Why? Still transparent, so it follows the new $D$ .
t3: $E=0$ → $Q$ holds $=1$ . Why? Cover closed; $D=0$ is ignored.
t4: $E=0$ → $Q$ holds $=1$ . Why? Still latched; the $D=1$ change is invisible.
t5: $E=1$ → $Q=D=1$ . Why? Re-opened; grabs current $D$ .

Final $Q$ row: 0 1 1 1 1.

5. Common mistakes (Steel-man + fix)

6. Active recall

Recall Quick self-test (hide answers)

What are the two states of a D latch and their names? → transparent ( $E=1$ , $Q=D$ ) and opaque/hold ( $E=0$ , $Q=Q_{prev}$ ).
Write the characteristic equation. → $Q_{next}=ED+\overline E Q$ .
How does the D latch remove the forbidden state? → sets $S=D,\ R=\overline D$ , so $S,R$ can't both be 1.
Latch vs flip-flop trigger? → level vs edge.

Recall Feynman: explain to a 12-year-old

Imagine a fridge with a magnetic note holder and a little lever. When you flip the lever on, whatever note you push against it sticks and shows up — and if you swap the note, the new one shows. When you flip the lever off, the last note stays frozen there, and even if you wave new notes in front, nothing changes. The lever is the enable, the note is the data D, and the note currently showing is Q. That's a D latch: it copies while the lever is on, and remembers while it's off.

7. Connections

SR Latch — the building block the D latch is made from.
NOR and NAND Gates — cross-coupled to form the storage loop.
D Flip-Flop — edge-triggered upgrade of this latch (master-slave uses two D latches).
Multiplexers — the 2:1 MUX view of the characteristic equation.
Clocking and Timing — why level-triggered latches cause transparency/glitch issues.
Registers — many D flip-flops in parallel.

What is a D latch?

A one-input storage element where

Q=D

when enable

E=1

(transparent) and

Q

holds its last value when

E=0

(opaque).

Characteristic equation of a D latch?

Q_{next} = E\,D + \overline{E}\,Q

How does the D latch eliminate the SR forbidden state?

It ties

S=D

and

R=\overline D

, so

S

and

R

are always opposite and can never both be 1.

Latch vs flip-flop: what's the trigger difference?

Latch is level-triggered (transparent while enable is high); flip-flop is edge-triggered (captures only on a clock edge).

What does a gated SR latch add over a plain SR latch?

An enable line that ANDs with S and R, so the latch only responds when enabled and holds otherwise.

When

E=0

, what does a D latch output?

It holds (remembers) its previous

Q

— it does NOT go to 0.

The D latch equation looks like which combinational block?

A 2:1 multiplexer with select

=E

, inputs

Q

and

D

, output fed back.

What does "transparent latch" mean?

While enabled, output follows input directly, as if data passes straight through.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, D latch samajhne se pehle SR latch ka problem samajh lo. SR latch me do inputs hote hain — Set aur Reset. Agar dono ek saath 1 ho jaayein to "forbidden state" ban jaati hai, output confuse ho jaata hai. Aur doosri problem — SR latch har waqt inputs sunta rehta hai, to circuit me chhote glitches se galat flip ho sakta hai. In dono problems ka solution hai gated latch aur D latch.

Gated latch me hum ek enable (E) wire add karte hain. Jab $E=1$ hai tabhi latch inputs ko sunta hai; jab $E=0$ hai to latch bas apni purani value hold karta hai — matlab yaad rakhta hai. Isse "kab sunna hai" ka control mil jaata hai. Phir D latch ek aur smart trick lagata hai: hum $S=D$ aur $R=\overline D$ set kar dete hain. Ab $S$ aur $R$ hamesha ulte rahenge, dono kabhi 1 nahi ho sakte, to forbidden state gayab! Sirf ek clean data bit $D$ store hota hai.

Iska magic formula yaad rakho: $Q_{next} = E\,D + \overline E\,Q$ . Iska matlab seedha hai — "agar enable on hai to $D$ le lo, warna purana $Q$ hold karo." Yeh bilkul ek 2:1 multiplexer jaisa hai jiska select line $E$ hai. Jab $E=1$ latch transparent ho jaata hai (output = input directly), aur jab $E=0$ to opaque ho jaata hai (yaad rakhta hai).

Sabse important galti jo students karte hain: yeh sochna ki $E=0$ pe output 0 ho jaata hai — nahi bhai, $E=0$ pe output hold hota hai, purani value bachi rehti hai, wahi to memory ka point hai! Aur ek aur — D latch aur D flip-flop same nahi hain. Latch level-triggered hai (jab tak $E=1$ hai transparent rehta hai), flip-flop edge-triggered hai (sirf clock ke edge pe capture karta hai). Yeh difference exam me bahut poocha jaata hai.