Worked examples — D latch and gated latches

Everything rests on one equation from the parent:

Here $E$ is the enable ("eyes open"), $D$ is the data bit we offer, $Q$ is what the latch currently shows, and $Q_{\text{next}}$ is what it shows after this instant. Every value is either $0$ or $1$ — nothing else exists in this world.

The scenario matrix

Every D-latch situation is one of these case classes. The examples that follow each hit one or more cells — the label tells you which.

We now walk them all.

Example 1 — Cells A & B: transparent tracking

Steps.

1. Apply the law at tick 1: $E=1$, so $Q_{\text{next}}=1\cdot D+0\cdot Q=D=0$. Why this step? With $E=1$ the term $\overline{E}Q=0$ vanishes, so the old $Q$ has no influence — only $D$ matters.
2. Tick 2: $D=1\Rightarrow Q=1$. Tick 3: $D=1\Rightarrow Q=1$. Tick 4: $D=0\Rightarrow Q=0$. Tick 5: $D=1\Rightarrow Q=1$. Why this step? Same reasoning repeats — while transparent, $Q$ is $D$, live and with no memory.

So $Q=0,1,1,0,1$ — an exact copy of $D$.

Verify: the $Q$ row equals the $D$ row cell-for-cell. That is the signature of a fully-transparent latch (Cell A when $D$ steady, Cell B when it changes). Look at the figure: the amber $Q$ trace sits on top of the cyan $D$ trace while $E$ (white) is high.

Example 2 — Cells B & C: transparent then opaque (the classic trap)

Steps.

1. Tick 1: $E=1,D=0\Rightarrow Q=1\cdot 0+0\cdot 0=0$. Why this step? Transparent (Cell B): copy $D$.
2. Tick 2: $E=1,D=1\Rightarrow Q=1$. Why this step? Still transparent — output chases the new $D$.
3. Tick 3: $E=0,D=0$. Now $Q_{\text{next}}=0\cdot 0+1\cdot Q_{\text{prev}}=Q_{\text{prev}}=1$. Why this step? Cell C. Enable is low, so $ED=0$ kills the data term entirely — $D=0$ is ignored, and $\overline{E}Q$ keeps the stored $1$.
4. Tick 4: $E=0,D=1$. Again $Q_{\text{next}}=Q_{\text{prev}}=1$. Why this step? Still opaque. Even though $D$ rose to $1$, the latch cannot see it. This is the trap: people expect $Q$ to follow $D$ here — it does not.
5. Tick 5: $E=1,D=1\Rightarrow Q=1$. Why this step? Re-opened (Cell B): grab current $D$.

So $Q=0,1,1,1,1$.

Verify: matches the parent note exactly. Sanity check the tricky tick 3 by the boxed formula with $E=0,D=0,Q_{\text{prev}}=1$: $0\cdot 0+1\cdot 1=1$. ✓ In the figure, notice the flat amber $Q$ across ticks 3–4 while the cyan $D$ wiggles beneath it — the visual proof that $D$ is being ignored.

Example 3 — Cells D & E: the two enable edges

Steps.

1. Tick 1: $E=0,D=1\Rightarrow Q=0\cdot 1+1\cdot 0=0$. Why this step? Still opaque — $D=1$ is offered but ignored; $Q$ stays $0$.
2. Tick 2 (opening edge $0\to 1$, Cell D): $E=1,D=1\Rightarrow Q=1\cdot 1=1$. Why this step? The instant the eyes open, the latch copies whatever $D$ is right now ($=1$). This is the "grab."
3. Tick 3 (closing edge $1\to 0$, Cell E): $E=0\Rightarrow Q=\overline{E}{Q}_{\text{prev}}=1$. Why this step? The eyes shut and $Q=1$ is frozen. Even if $D$ later dropped, this stored $1$ would survive.

So $Q=0,1,1$.

Verify: the value stored after closing equals the value present at the moment before closing ($D=1\Rightarrow Q=1$). That's the defining property of a transparent latch — it captures the last transparent value, not a fresh one. Units check: everything is $\{0,1\}$, no illegal value appeared.

Example 4 — Cells F & G: the two degenerate extremes

Steps.

1. Case F: substitute $E=1$ (so $\overline{E}=0$) permanently: $Q_{\text{next}}=1\cdot D+0\cdot Q=D.$ Why this step? With $E$ pinned high the memory term dies. The output is always $D$ — the latch is now just a piece of wire (or a buffer). No storage at all.
2. Case G: substitute $E=0$ (so $\overline{E}=1$) permanently: $Q_{\text{next}}=0\cdot D+1\cdot Q=Q.$ Why this step? With $E$ pinned low the data term dies. $Q$ equals its own previous value forever — a frozen bit that can never change. Whatever it powered up as, it stays.

Verify: these are the two rows of the truth table taken to their limits. Plug numbers: F with $D=0$ gives $Q=0$, with $D=1$ gives $Q=1$ (pure copy ✓). G with any $D$ returns $Q_{\text{prev}}$ (pure hold ✓). Both degenerate cases fall straight out of the same one equation — a good sign the equation is complete.

Example 5 — Cell H: a glitch sneaks through while transparent

Steps.

1. Tick 1: $E=1,D=0\Rightarrow Q=0$. Why this step? Transparent, copy the clean $0$.
2. Tick 2: $E=1,D=1\Rightarrow Q=1$. Why this step? Cell H. Because $E=1$, the latch has no way to distinguish a real value from a glitch — it dutifully copies the spike. $Q$ momentarily goes wrong.
3. Tick 3: $E=1,D=0\Rightarrow Q=0$. Why this step? Transparent again; $Q$ follows $D$ back down.

So $Q=0,1,0$ — the glitch passed straight through.

Verify: compare to Example 2 tick 3–4, where the same $D$-change was ignored because $E=0$. The only difference is enable. Conclusion: a latch is safe against $D$ glitches only while opaque. This is exactly why designers prefer edge-triggered flip-flops (which sample $D$ at a single clock instant) and why Clocking and Timing matters. See the figure: the amber $Q$ spike copies the cyan $D$ spike because white $E$ is high throughout.

Example 6 — Cell I: real-world word problem

Steps.

1. Map the hardware: $E$ = button, $D$ = coin sensor, $Q$ = LOCKED light. Start $Q=0$ (unlocked). Why this step? Word problems are just the same equation with real names glued on.
2. Button pressed while coin present ($E=1,D=1$): $Q=1\cdot 1=1$. Light turns on. Why this step? Transparent open (Cell D) copies the coin's $1$.
3. Coin removed before button released ($E=1,D=0$): $Q=1\cdot 0=0$. Light goes off — bad! Why this step? Cell B — while transparent, removing the coin drops $Q$. The design is fragile if the coin leaves first.
4. Correct operating order — release button first ($E:1\to 0$ while $D=1$), then remove coin: after release $Q=\overline{E}Q=1$; removing coin ($E=0,D=0$) still gives $Q=1$. Why this step? Cell E freezes the $1$, and Cell C ignores the subsequent coin removal. Light stays on.

Verify: the answer depends on ordering, which is precisely the transparency hazard. If the button releases first, $Q$ latches $1$ and survives coin removal ($0\cdot 0+1\cdot 1=1$ ✓). If the coin leaves first, $Q$ follows to $0$ ($1\cdot 0+0\cdot 1=0$ ✓). Both traced with the one equation — no contradiction.

Example 7 — Cell J: trust the algebra, ignore intuition

Steps.

1. Substitute $E=1,\overline{E}=0,D=1,Q=0$: $Q_{\text{next}}=(1)(1)+(0)(0)=1+0=1.$ Why this step? Boolean $+$ is OR, boolean $\cdot$ is AND. $1\cdot 1=1$ and $0\cdot 0=0$; $1\text{ OR }0=1$.
2. Now test the opposite corner to be safe: $E=0,\overline{E}=1,D=1,Q=0$: $Q_{\text{next}}=(0)(1)+(1)(0)=0.$ Why this step? Confirms that with $E=0$ the $D=1$ is rejected — the equation alone encodes the hold behaviour; no picture needed.

Verify: both results match Examples 1 and 3 respectively. The equation is a complete description — every one of the four $(E,D)$ input pairs, with either starting $Q$, is determined by it. That is why we can trust it in exams over shaky intuition.

Example 8 — Cell K: inverted enable and the $\overline{Q}$ output

Steps.

1. Translate active-low to our standard $E$: the real enable is $E=\overline{\overline{EN}}=\text{NOT}(\overline{EN})$. Here $\overline{EN}=0\Rightarrow E=1$. Why this step? Our master equation uses "high = transparent." An active-low pin must be inverted first, or every sign flips.
2. Now standard law: $E=1,D=1\Rightarrow Q=1\cdot 1+0\cdot 0=1$. Why this step? Transparent — copy $D$.
3. Complement output: $\overline{Q}=\text{NOT}(Q)=\text{NOT}(1)=0$. Why this step? $\overline{Q}$ is always the opposite of $Q$ by construction — it's the second wire of the internal cross-coupled pair from SR Latch.

So $Q=1,\overline{Q}=0$.

Verify: $Q$ and $\overline{Q}$ are complements ($1$ and $0$) — never equal, which is exactly the property the D-trick guarantees (it removed the forbidden state where both could be $0$). If we had blindly used $\overline{EN}$ as $E$ we'd have gotten $E=0$ (hold) and answered $Q=0$ — wrong. The sign bookkeeping mattered.

Coverage check — did we hit every cell?

Connections

• D latch and gated latches — the parent rules these examples exercise.
• SR Latch — source of the $Q,\overline{Q}$ complement pair (Ex 8).
• NOR and NAND Gates — the internal cross-coupled loop.
• D Flip-Flop — edge-triggered fix for the glitch of Ex 5.
• Clocking and Timing — why transparency (Ex 5, Ex 6) is dangerous.
• Multiplexers — the 2:1 MUX view behind Ex 7's equation.
• Registers — many such latches/flip-flops in parallel.