Exercises — D latch and gated latches

When $E=1$ the latch is transparent: the output simply copies $D$. $Q_{\text{next}}=ED+\overline{E}Q=(1)(0)+(0)(1)=0.$ Answer: $Q_{\text{next}}=0$. The old $Q=1$ is overwritten because the "door is open."

$E=0$ means hold (opaque). The new $D=1$ is ignored. $Q_{\text{next}}=(0)(1)+(1)(0)=0.$ Answer: $Q_{\text{next}}=0$ — the latch keeps its old value, it does not copy $D$.

True. Internally the D latch wires $S=D$ and $R=\overline{D}$. Since $D$ and $\overline{D}$ are always opposite, $S$ and $R$ can never both be 1. The forbidden state is designed out.

Apply $Q_{\text{next}}=ED+\overline{E}Q$ column by column, carrying $Q$ forward.

• t1: $E=1$ → transparent → $Q=D=0$.
• t2: $E=0$ → hold → $Q=0$ (ignore $D=1$).
• t3: $E=0$ → hold → $Q=0$.
• t4: $E=1$ → transparent → $Q=D=1$.
• t5: $E=1$ → transparent → $Q=D=0$ (follows the new $D$ immediately — this is the "transparency" you can see in the waveform below).
• t6: $E=0$ → hold → $Q=0$.

Answer row: 0 0 0 1 0 0.

Look at the green $Q$ line: while $E$ is high (shaded bands) $Q$ chases $D$; while $E$ is low it flat-lines.

Compare $Q$ (from 2.1) with $D$ each step:

Answer: 4 steps ($t=1,3,4,5$). Note that steps where they happen to match while holding (t3) still count as equal, but the cause differs — only during $E=1$ is the equality guaranteed.

Track the "old $Q$" (call it $Q_{\text{prev}}$) and reason step by step.

• t1: $Q_{\text{prev}}=0$, output became $1$. Only $E=1$ can produce $Q=D=1$; holding would keep $0$. → $E=1$.
• t2: $Q_{\text{prev}}=1$, $D=0$, output stayed $1$. If $E=1$ we'd get $Q=D=0$ — wrong. So we must hold → $E=0$.
• t3: $Q_{\text{prev}}=1$, $D=1$, output $1$. Both work: $E=1$ gives $D=1$; $E=0$ holds $1$. → $E=0$ or $1$.
• t4: same as t3 ($Q_{\text{prev}}=1$, $D=1$, out $1$) → $E=0$ or $1$.

Answer: $E=1,0,(\text{either}),(\text{either})$. The forced values are $E_1=1,E_2=0$.

A 2:1 MUX with select $S$ outputs $\text{MUX}=\overline{S}{I}_0+S{I}_1$. Substitute $S=E,I_0=Q,I_1=D$: $\text{MUX}=\overline{E}Q+ED.$ By commutativity of OR this is identical to $ED+\overline{E}Q$. Proven. So a D latch is literally a 2:1 MUX with its own output $Q$ fed back into input-0.

Put one inverter on the enable pin: feed $E=\overline{EN}$ into the standard latch. Then transparency ($E=1$) happens exactly when $EN=0$. Substitute $E=\overline{EN}$ into the master equation: $Q_{\text{next}}=\overline{EN}D+ENQ.$ Check: $EN=0$ → $Q_{\text{next}}=1\cdot D+0\cdot Q=D$ (transparent). $EN=1$ → $Q_{\text{next}}=0+1\cdot Q=Q$ (hold). ✓ Minimum extra hardware = one NOT gate.

We want: $T=1\Rightarrow Q_{\text{next}}=\overline{Q}$ (flip); $T=0\Rightarrow Q_{\text{next}}=Q$ (hold). This is exactly XOR: $D=T\oplus Q.$ Feed that into the latch (with $E$ pulsed). Verify:

• $T=0$: $D=0\oplus Q=Q$ → stores $Q$ → hold. ✓
• $T=1$: $D=1\oplus Q=\overline{Q}$ → stores $\overline{Q}$ → flip. ✓

Answer: $D=T\oplus Q$, i.e. an XOR gate between the control $T$ and the fed-back output $Q$. (Note: with a level-triggered latch this would oscillate while $E$ is high — see the L4 trap. A proper toggle needs an edge-triggered D Flip-Flop.)

D latch (level-triggered): because it is transparent while $E=1$, $Q$ copies $D$ continuously. So $Q$ goes $0\to 1\to 0$ — the glitch passes straight through to the output. This is the danger of transparency (Clocking and Timing).

D flip-flop (edge-triggered): it only samples $D$ at the clock edge. If no edge occurs during the glitch, $Q$ is unaffected — it captured whatever $D$ was at the last edge. This edge-rejection is exactly why registers are built from flip-flops, not latches (Registers).

Answer: latch passes the glitch; flip-flop (if the glitch misses the edge) rejects it.

Trace ($Q$ starts at 0):

• t1: $E=1$ → $Q=D=1$.
• t2: $E=1$ → $Q=D=0$.
• t3: $E=0$ → hold → $Q=0$.
• t4: $E=1$ → $Q=D=1$.
• t5: $E=0$ → hold → $Q=1$.

Answer row: 1 0 0 1 1.

Cross-check t4 with $Q_{\text{next}}=ED+\overline{E}Q$, using $E=1,D=1,Q_{\text{prev}}=0$: $Q_{\text{next}}=(1)(1)+(0)(0)=1✓$ Matches the trace → both methods agree.

Each latch obeys its own copy of the master equation: $Q_1=E{D}_1+\overline{E}{Q}_1^{\text{prev}},Q_0=E{D}_0+\overline{E}{Q}_0^{\text{prev}}.$ While $E=1$ both are transparent, so they load $Q_1=D_1=1,Q_0=D_0=0$. When $E$ drops to $0$, both freeze at that value. Answer: stored value $Q_1{Q}_0=10$ (decimal 2). This 2-bit array of latches sharing one enable is the seed idea behind a register.

• $E=0$, any $D$: output? ::: holds previous $Q$.
• D latch as a MUX: select, input-0, input-1? ::: select $=E$, input-0 $=Q$, input-1 $=D$.
• $D=T\oplus Q$ builds what behaviour? ::: toggle when $T=1$, hold when $T=0$.
• Why does a glitch pass through a latch but not a flip-flop? ::: latch is transparent (level), flip-flop samples only at an edge.