D latch and gated latches: Visual walkthrough — Hardware deep dive

Step 0 — The alphabet (what the symbols even mean)

Before any circuit, let us agree on the tiny language we will use. In digital hardware every wire carries exactly one of two values.

Now three named wires we will keep for the whole page:

$D$ — the data wire. The single bit you want to store.
$E$ — the enable wire. A gate: it decides whether the latch is listening.
$Q$ — the output wire. The bit the latch is currently showing / remembering.

And three tiny operations, each of which is a physical gate (a little box you can build):

The dot $\cdot$ is AND, the plus $+$ is OR, the bar is NOT. That is the entire alphabet. Everything below is spelled with these letters.

Step 1 — The starting point: a latch that remembers

WHAT. We begin with the thing from SR Latch: two cross-coupled gates that can stay in a state after you let go. Think of it as a lamp that, once lit, keeps itself lit — it has memory. Its stored bit is what we call $Q$ .

WHY. A plain logic gate forgets instantly: change the input, the output changes, no history. To store a bit we need feedback — the output loops back and reinforces itself. That loop is the source of memory. Without it, there is no "remember", and the entire idea of a latch collapses.

PICTURE. Below, the output $Q$ curves back into the box that produced it (the pink feedback arrow). That returning arrow is literally "yesterday's answer coming back to influence today". Hold that image — the loop is why $Q$ can appear on the right-hand side of our final equation.

The raw SR latch has two inputs, $S$ (set → force $Q = 1$ ) and $R$ (reset → force $Q = 0$ ), and one villain: if $S = R = 1$ it breaks (the forbidden state). We will now cage it.

Step 2 — The gate: making the latch listen only when told

WHAT. We insert one AND gate on each input. Instead of raw $S$ and $R$ reaching the memory loop, we feed it $S^{'} = S \cdot E$ and $R^{'} = R \cdot E$ .

WHY. AND is the perfect "permission" gate. Recall from Step 0: $A \cdot B$ is 1 only if both are 1. So $S \cdot E$ can only be 1 when $E = 1$ . The moment $E = 0$ , both $S^{'}$ and $R^{'}$ are forced to 0 no matter what the outside world screams. Zero on both set and reset means "hold" — the latch ignores everyone and keeps $Q$ . This is the whole trick of the gate idea: use AND as a valve.

PICTURE. In the drawing, $E$ is the blue "eyes" wire. When it is dark ( $E = 0$ ) the two AND valves are shut and the outside inputs cannot get through — the loop is sealed. When $E$ is lit ( $E = 1$ ) the valves open and $S, R$ flow to the loop.

what reaches the loop S^{'} = outside request S \cdot permission E R^{'} = R \cdot E

Each $\cdot$ here means "the request only counts if permission $E$ is also 1."

We now control when. But $S$ and $R$ are still independent, so the forbidden $S = R = 1$ can still happen. Step 3 kills it.

Step 3 — The one-wire trick: deleting the forbidden state

WHAT. We stop letting the user drive $S$ and $R$ separately. Instead we grow both of them from a single data wire $D$ : $S = D, R = \overline{D} .$

WHY. Look at what $\overline{D}$ (NOT- $D$ , from Step 0) guarantees. If $D = 1$ then $\overline{D} = 0$ ; if $D = 0$ then $\overline{D} = 1$ . They are always opposite. So $S$ and $R$ can never both be 1 — the forbidden combination is now physically unreachable. We did not "avoid" the bad state by being careful; we built it out of existence.

PICTURE. A single wire $D$ enters, splits, and one branch passes through a NOT box before becoming $R$ . The two resulting arrows always point opposite ways (one lit, one dark). Notice you cannot make them both lit — the NOT box forbids it.

set S = the data bit D reset R = the *opposite* of the data bit \overline{D}

Combine Step 2 and Step 3: our latch now receives $S^{'} = D \cdot E$ and $R^{'} = \overline{D} \cdot E$ . One data pin, one enable pin, no villain. This is the D latch.

Step 4 — Case $E = 1$ : the latch is transparent

WHAT. Set the enable high, $E = 1$ , and read off what $Q$ becomes for each value of $D$ .

WHY. With $E = 1$ , the AND valves are fully open, so $S^{'} = S = D$ and $R^{'} = R = \overline{D}$ (anything AND 1 is itself). We just apply the plain SR rules from Step 1:

$D = 1$ : then $S^{'} = 1, R^{'} = 0$ → set → $Q = 1$ .
$D = 0$ : then $S^{'} = 0, R^{'} = 1$ → reset → $Q = 0$ .

In both rows, $Q$ ends up equal to $D$ . The output is a live copy of the input — we call this transparent, like looking through clear glass straight at $D$ .

PICTURE. Two side-by-side snapshots. Left: $D$ lamp lit → $Q$ lamp lit. Right: $D$ lamp dark → $Q$ lamp dark. $Q$ mirrors $D$ exactly while the blue enable stays lit.

E = 1 ⟹ Q_{next} = D

Step 5 — Case $E = 0$ : the latch is opaque (it remembers)

WHAT. Now drop the enable, $E = 0$ , and see what happens to $Q$ regardless of $D$ .

WHY. With $E = 0$ , both valves shut: $S^{'} = D \cdot 0 = 0$ and $R^{'} = \overline{D} \cdot 0 = 0$ (anything AND 0 is 0). Set=0 and Reset=0 is exactly the hold command from Step 1. The feedback loop from Step 1 keeps re-lighting itself, so $Q$ stays frozen at whatever it was:

E = 0 ⟹ Q_{next} = Q (the old value, unchanged) .

Change $D$ all you like — it is walled off by the shut valves. This is the opaque state: the glass is now painted over; you see the last thing that was written, not the live $D$ .

PICTURE. The blue enable is dark. Both AND valves are shut (drawn as broken paths). The pink feedback loop is highlighted — it is the only thing now driving $Q$ , holding it steady. Wiggling $D$ (shown greyed-out) has no effect.

Step 6 — Gluing both cases into one equation

WHAT. We have two separate facts:

E = 1 \Rightarrow Q_{next} = D, E = 0 \Rightarrow Q_{next} = Q .

We want a single boolean expression that produces $D$ in the first case and $Q$ in the second, automatically.

WHY this tool — the "OR of two guarded terms". This is a standard trick: build one term that is "alive" only when $E = 1$ , another that is "alive" only when $E = 0$ , and OR them. Exactly one term is ever awake, so the OR just passes it through.

Term for the enabled case: $E \cdot D$ . When $E = 1$ this equals $D$ ; when $E = 0$ it collapses to 0 (asleep).
Term for the hold case: $\overline{E} \cdot Q$ . When $E = 0$ , $\overline{E} = 1$ so this equals $Q$ ; when $E = 1$ , $\overline{E} = 0$ so it collapses to 0 (asleep).

Because $E$ and $\overline{E}$ are opposites (Step 0), never both terms are awake at once — so the OR $+$ never has to decide between two competing 1's. It simply forwards whichever term is alive.

Q_{next} = awake when E = 1, gives D E \cdot D + awake when E = 0, gives old Q \overline{E} \cdot Q

Reading each symbol where it sits: $E \cdot D$ = "if enabled, take the data"; the $+$ = "or else"; $\overline{E} \cdot Q$ = "keep the old output". That is the parent's boxed result, now derived, not asserted:

PICTURE. The two terms drawn as two lanes merging into an OR. A little switch labelled $E$ picks the live lane — literally the MUX view of the storage cell.

Step 7 — Sanity check: every case, no gaps

Let us make sure the one equation reproduces all four input rows. Plug into $Q_{next} = E D + \overline{E} Q$ :

$E$	$D$	old $Q$	$E D$	$\overline{E} Q$	$Q_{next}$	meaning
1	1	0	1	0	1	transparent → copies $D$
1	0	1	0	0	0	transparent → copies $D$
0	1	0	0	0	0	hold old $Q$ (ignores $D = 1$ )
0	0	1	0	1	1	hold old $Q$ (ignores $D = 0$ )

Every combination lands on the intended behaviour, and there is no forbidden row — Step 3 deleted it. Notice the degenerate check: when $E = 0$ the value of $D$ never touches the answer (both $D = 0$ and $D = 1$ hold the same $Q$ ), confirming the "opaque" claim from Step 5.

The one-picture summary

Below, the whole journey on one board: $D$ splits (Step 3) → AND valves gated by $E$ (Step 2) → cross-coupled memory loop (Step 1) → and the equivalent MUX-with-feedback view (Step 6), with the two behaviour lamps (Steps 4–5) shown as the outcome.

Recall Feynman retelling — the walkthrough in plain words

We started with a lamp that can keep itself lit — that is memory, the loop that sends yesterday's answer back into today ( $Q$ ). Raw, it had two buttons, set and reset, and a nasty fault if you press both. First we put a valve (an AND gate) on each button controlled by a single eyes-open wire $E$ : eyes shut, no button reaches the lamp, so it just remembers. Then we did the clever bit: instead of two independent buttons we grew both from one data wire $D$ — one button gets $D$ , the other gets the opposite of $D$ — so they can never both be pressed, and the fault is gone forever. Now: eyes open ( $E = 1$ ) and the lamp becomes a live mirror of $D$ (transparent); eyes shut ( $E = 0$ ) and the lamp freezes on its last value (opaque). Finally we packed both stories into one sentence of algebra: $E D$ is "when watching, show the data", $\overline{E} Q$ is "otherwise keep the old picture", and the $+$ glues them — with $E$ and its opposite guaranteeing exactly one story is ever awake. That single line, $Q_{next} = E D + \overline{E} Q$ , is the whole D latch.

Connections

SR Latch — the memory loop we started from in Step 1.
NOR and NAND Gates — the physical gates behind the loop and the valves.
Multiplexers — the Step 6 select-and-forward view.
D Flip-Flop — chain two of these to get an edge-triggered cell.
Clocking and Timing — why "transparent while $E = 1$ " (Step 4) causes glitch worries.
Registers — many such cells side by side.

Why can the D latch never hit the SR forbidden state?

Because

S = D

and

R = \overline{D}

are always opposite, so both can never be 1.

In the equation

Q_{n e x t} = E D + \overline{E} Q

, what does each term do?

E D

is awake only when

E = 1

and passes

D

;

\overline{E} Q

is awake only when

E = 0

and passes the old

Q

What makes exactly one term of the characteristic equation active at a time?

E

and

\overline{E}

are opposites, so never both are 1 — the OR forwards whichever term is alive.