E = enable ("eyes open"). D = data being shown. Q = what's currently stored. Transparent = eyes open, Q copies D. Opaque = eyes closed, Q frozen. Keep the equation Qnext=ED+EQ in view.
Before the traps, lock in four images. Every trick below is really testing whether you see one of these.
1. What lives inside a D latch. The one external data pin D splits into two internal wires: the Set line S and the Reset line R. We force S=D and R=D (the little bubble means "NOT"), so they are always opposites. These feed an inner SR Latch whose job is to store the bit. The enable E gates them.
2. What "forbidden" actually does. A NOR-based SR latch computes each output as NOR of (the input, the other output). When S=R=1, both outputs are forced to 0 at once — but Q and Q are supposed to be opposites, so this is a contradiction. Worse, when S and R drop back to 0 together, the two gates race and the final value is unpredictable. That whole scenario is the forbidden state, and the D trick makes it unreachable.
3. The MUX view of the equation.Qnext=ED+EQ is literally a 2-to-1 multiplexer: the select line is E, input-0 is the old Q fed back on itself, input-1 is the new D. E just picks which door the output comes from.
4. The timing waveform. "Transparent," "hold," and "the moment E falls" are all time behaviours — so they only make sense as a waveform. Watch how Q copies D while E is high, then freezes flat the instant E goes low.
True — it has a single data pin D, so at any moment it holds one binary value in Q; stack many of them and you get a register holding a whole byte.
When E=0 the output of a D latch is 0.
False — E=0 means hold, so Q keeps whatever it last stored; the equation gives EQ=1⋅Q=Q, not 0 (see the flat frozen segment in figure s04).
A D latch can enter the forbidden state if D glitches.
False — internally S=D and R=D are always opposites (figure s01), so S=R=1 is structurally impossible no matter how D behaves.
While E=1, changing D changes Q immediately.
True — that is the definition of transparent: the output tracks D continuously the whole time the enable is high (figure s04, the copy region), not just once.
A gated SR latch fully removes the forbidden combination.
False — it only controls when the latch listens; with E=1,S=1,R=1 the forbidden state of figure s02 still occurs. Only the D trick removes it.
Error: E=0 is hold, not reset. There is no reset action; Q retains its stored value. Confusing "disabled" with "cleared" is the classic slip.
"We can drive S and R separately on a D latch for more control."
Error: as figure s01 shows, R=D is derived from the single pin D; there is no independent S/R access from outside. That independence was deliberately thrown away to kill the forbidden state.
"The D latch equation is Qnext=ED."
Error: this drops the hold term. When E=0 it would force Q=0, destroying the memory. The correct form adds EQ so the old value survives.
"A NOR-based SR latch holds when S=R=1."
Error: S=R=1 is the forbidden case of figure s02 (both outputs go to 0); the hold case is S=R=0. See SR Latch.
"Since the latch is transparent while enabled, glitches on D don't matter."
Error: transparency is exactly why glitches matter — any spike on D while E=1 passes straight through to Q (figure s04's copy region tracks D exactly). This is a core motivation for edge-triggered Clocking and Timing.
"A D latch built from NAND gates needs S=D instead of S=D."
Error: the mapping S=D,R=D is about logic, not gate family; NAND implementations may invert internal signals but the external behaviour Qnext=ED+EQ is unchanged. See NOR and NAND Gates.
Because a bare latch reacts to inputs at all times, so slightly-mistimed real-world signals flip it randomly; the enable lets us choose when the latch is allowed to change.
Why does tying R=D eliminate the forbidden state?
Because D and D can never be 1 at the same time, so the internal set and reset lines are always opposites — the one combination (figure s02) that broke the SR latch is now unreachable.
Why is a D latch called "transparent"?
Because while E=1 you can "see through" it — the output is just a copy of the input, as if the storage element weren't there at all (figure s04).
Why does the characteristic equation prove the latch has memory?
The EQ term means the output feeds back into its own next value (the feedback wire in figure s03); a variable defined partly in terms of itself is precisely what "remembering the past" looks like in Boolean form.
Why can two D latches be combined to make a flip-flop?
A master-slave pair enables the two latches on opposite phases, so data passes through only at a clock edge instead of during a whole level — converting transparent behaviour into edge-triggered capture (see D Flip-Flop).
Why is level-triggering a problem in a feedback loop?
If the latch stays transparent, a changing output could race back around and change the input during the same enable window, causing unpredictable oscillation — the reason clocked, edge-triggered designs exist (Clocking and Timing).
Q toggles right along with D — the latch is fully transparent and simply mirrors every change (the wiggle in figure s04's copy region); it stores nothing stable until E returns to 0.
Starting from Q=1, apply E=0 then later E=0 with D=0 throughout — what is Q?
Q stays 1 the entire time; enable is never high, so the D=0 is ignored and the stored 1 is held.
At the exact moment E falls from 1 to 0, what value gets latched?
Whatever D was at that transition instant is frozen (the freeze point in figure s04); this is why D must be stable around the falling edge — otherwise the captured value is ambiguous (a timing/setup concern in Clocking and Timing).
Power-on: what is Q before any E=1 pulse ever occurs?
Undefined — a latch has no inherent starting value, so it powers up in an arbitrary 0 or 1; real designs add an explicit reset for this reason.
If E is stuck at 0 forever due to a fault, how does the latch behave?
It becomes a frozen memory: it keeps its power-on value permanently and ignores every D change, since it can never enter the transparent state.
If both E=1 and D are held constant, is the latch still "storing"?
Functionally no — Q merely equals the fixed D; genuine storage (holding a value against a changing input) only happens once E=0.