D latch and gated latches

3.4.2 · Hardware › Sequential Circuits

1. Humein yeh kyun chahiye? (SR latch ki problem se)

Yeh bura kyun hai? Do problems hain:

1. Forbidden state $S=R=1$ mein $Q$ aur $\overline{Q}$ dono equal ho jaate hain — ek contradiction — aur final state ek race condition hoti hai.
2. Latch inputs par turant aur har waqt react karta hai. Real circuit mein signals thodi alag timing par aate hain ("glitches"), aur latch randomly flip ho jaata.

Hum #2 ko gate/enable se solve karte hain, aur #1 ko D trick se.

2. Gated SR Latch — ek control wire add karna

Yeh kaise bana hai: SR latch lo, aur use $S^{\prime }=S\cdot E$ aur $R^{\prime }=R\cdot E$ feed karo.

$Q_{\text{next}}=\{\begin{array}{ll}\text{hold}& E=0\\ \text{SR behaviour}(S,R)& E=1\end{array}$

Progress! Ab hum control karte hain kab. Lekin forbidden state abhi bhi exist karta hai. Ab aata hai D latch.

3. D Latch — forbidden state ka khatma

First principles se next-state equation derive karna:

Gated SR latch se shuru karte hain jahan $S=D$, $R=\overline{D}$:

• Agar $E=1$: $S^{\prime }=D,R^{\prime }=\overline{D}$.
  • $D=1\Rightarrow S^{\prime }=1,R^{\prime }=0\Rightarrow Q=1$
  • $D=0\Rightarrow S^{\prime }=0,R^{\prime }=1\Rightarrow Q=0$
  • Toh $Q_{\text{next}}=D$.
• Agar $E=0$: $S^{\prime }=R^{\prime }=0\Rightarrow$ hold, toh $Q_{\text{next}}=Q$.

Dono cases ko EK boolean expression mein combine karna:

$\boxed{Q_{\text{next}}=E\cdot D+\overline{E}\cdot Q}$

4. Worked examples

5. Common mistakes (Steel-man + fix)

6. Active recall

7. Connections

• SR Latch — woh building block jisse D latch bana hai.
• NOR and NAND Gates — storage loop banane ke liye cross-coupled hote hain.
• D Flip-Flop — is latch ka edge-triggered upgrade (master-slave mein do D latches use hote hain).
• Multiplexers — characteristic equation ka 2:1 MUX view.
• Clocking and Timing — kyun level-triggered latches transparency/glitch issues paida karte hain.
• Registers — parallel mein kai D flip-flops.

Concept Map