Intuition The one core ideaAn SR latch is two logic gates wired so that each gate's output becomes the other gate's input — a loop that props itself up. Once you understand what a gate is, what "feedback" means, and what the little bar over Q
Before you can read a single line of the parent note, you need a small toolbox of ideas. This page builds every one of them from absolute zero , in an order where each idea leans on the one before it — exactly like the two kids leaning on each other.
A bit is a value that can be only one of two things. We write those two things as 0 and 1. In hardware, 0 is usually "low voltage" and 1 is "high voltage".
Intuition Picture it as a light switchThink of a switch on the wall: it is either down (0) or up (1) . There is no "half up". Everything digital is built from millions of these two-state switches. The whole point of the SR latch is to be one switch that remembers where you last flicked it — even after your hand leaves.
A logic gate is a tiny circuit that takes one or more bits in and produces one bit out , following a fixed rule. Draw it as a box: arrows go in on the left, one arrow comes out on the right.
The rule never changes — the output only depends on what is at the inputs right now . That "right now" part matters a lot, so we give it a name.
A circuit is combinational if its output depends only on the present inputs . Remove the inputs → the output has nothing to stand on → it collapses. A lone gate is combinational: it has no memory .
The parent note's very first job is to escape this "no memory" trap. So hold that word — combinational — we will break it deliberately in section 5.
Before we can even write down the NOR rule, we must fix two pieces of notation, because in this world they do not mean what they mean in ordinary arithmetic.
+ + not mean ordinary addition. a + b OR : the result is 1 if at least one of a b 1. So 1 + 1 = 1 1 + 0 = 1 0 + 0 = 0 + as the word "or".
x NOT it — flip that value: 0 = 1 1 = 0 group like a + b
Common mistake The trap that catches everyone"1 + 1 = 2
There is no 2 in a world of bits. + here is OR , so 1 + 1 = 1 + inside these latch equations, say "or" out loud.
Now — and only now — every symbol we are about to use has a meaning. On to the gate itself.
The parent builds its main latch from NOR gates, so we must know NOR cold.
NOR = "NOT OR": take the OR of the inputs (section 2's + x
Here is that rule written out completely — a self-contained truth table, every possible input row shown:
a b a + b a + b
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
0
The same table is drawn as a figure so you can see the shape of the gate beside it:
Intuition Why this "any 1 forces 0" fact is the whole latch engineLook at the table: a single 1 on a NOR input dominates — it drags the output to 0 no matter what the other input is. In the latch, the control inputs (we will name them S R 1s: driving one to 1 forces one gate's output, which then releases the other gate. Everything the parent derives is this domino, twice.
The dual gate, NAND , works the mirror-opposite way (output is 0 only when both inputs are 1). The parent's NAND version is just this same domino with 0 and 1 swapping roles — see Cross-coupled gates for how the wiring is identical.
Q Q Q stored bit — the thing we call "the latch's value". Q Q = 1 Q = 0
Worked example Read one real latch equation slowlyWith Q Q = S + Q Q S Q S S = 1 1 + Q = 1 1 is always 1, from section 2), so Q = 1 = 0 1 dominated, exactly the NOR rule of section 3.
Intuition Why keep BOTH outputs?The latch is a loop, and a loop needs two ends to feed each other. Q Q and the other gate's input at the same time. That double-duty is the feedback (next section). Also, having the ready-made opposite Q
Q Q hope , not a law . The parent shows one forbidden case where both are 0 at once — genuinely not opposite. Names describe the intended behaviour, not a guarantee.
This is the keystone. Everything above was tools; this is the trick.
Feedback means a circuit's own output is wired back to become part of its own input . The output is no longer just a result — it is also a cause.
Intuition Why a loop can rememberA plain gate (section 1) forgets the moment inputs leave. But if the output loops back in, the circuit can reach a state where the value it outputs is exactly the value its own inputs need to keep outputting that value . It agrees with itself. Nothing pushes it to change, so it just... stays. That self-agreement is memory . The parent calls this a stable or self-consistent state — same thing.
Cross-coupled the other gate's input (they cross, like an X). Two gates crossed this way is the smallest possible memory loop — the SR latch.
This is precisely why the parent opens with "feed their outputs back into each other ". Now that sentence is fully unpacked.
Now we can finally name the two buttons that drive the latch.
S R S R control inputs of the latch. S Q = 1 R Q = 0 neither is driven, the latch just holds whatever it had.
Definition Active-HIGH / Active-LOWAn input is active-HIGH if a 1 is what triggers its action (the NOR latch's S R active-LOW if a 0 triggers it (the NAND latch's S R S
Common mistake The forbidden input: drivingS R S = 1 R = 1 both Q = 0 Q = 0 Metastability in section 7). For the NAND version the forbidden state is the mirror image: S = 0 R = 0
Mnemonic Which gate is which"NOR active hi, NAND active low" → "aNd goes dowN." NAND (the N-A-N-D one) pulls the active value down to 0.
Why does the parent bother with both flavours? Because real chips come in both, and later devices like the Gated SR latch , D latch , and JK flip-flop are all built on top of one of these two. Knowing that 0 and 1 simply swap roles saves you from re-learning the whole table.
The parent writes Q p r e v Q n e x t before and after .
Q p r e v Q n e x t state is the value the latch is currently holding. Q p r e v just before we apply new inputs; Q n e x t just after things settle. The whole "Hold" behaviour is the sentence Q n e x t = Q p r e v nothing changed .
Intuition Why we even need "prev" and "next"A combinational gate has no before/after — its answer is instant and dependent only on now. The moment we added feedback (section 5), the past started to matter, so we need labels for it. These two labels are the parent's whole reason for existing: a latch is a device where Q n e x t Q p r e v
One extra warning word you'll meet:
If both inputs illegally fire (the forbidden S = 1 , R = 1 0 and 1, like a coin landing on its edge, before randomly falling. That unstable in-between is Metastability why the "both active" input is forbidden.
Logic gate = input bits to output bit
Combinational = no memory
NOR rule = any 1 forces 0
Q and Q-bar = two outputs
Feedback = output wired to input
Cross-coupled = each feeds the other
State prev and next = time
S and R inputs active high or low
Read it bottom-up: every arrow is a "you need this first". The parent topic SR latch operation sits at the very end because it consumes all of them at once.
Recall Self-test: can you answer each before revealing?Tick these off — if any fails, re-read its section above.
What is a bit, physically? A two-state value, usually low voltage = 0 and high voltage = 1.
What does "combinational" mean, and why is it the enemy of memory? Output depends only on present inputs; remove inputs and the output vanishes — no storage.
In these equations, what does the symbol + OR — so 1 + 1 = 1
What does an overbar x Flips (NOT) whatever is under it, after evaluating the inside first.
State the NOR rule in one sentence. Output is 1 only when both inputs are 0; any input equal to 1 forces the output to 0.
What are Q Q Q Q The stored bit and its intended complement; the opposite relation holds only for legal inputs, not the forbidden one.
Define feedback and explain why it creates memory. Output wired back as input; the loop can settle into a state that keeps re-asserting itself, so it "remembers" after inputs leave.
What does "cross-coupled" mean? Each gate's output feeds the other gate's input, forming the smallest memory loop.
What do the inputs S R S (Set) forces Q=1, R (Reset) forces Q=0; neither driven means Hold.
Which input combination is forbidden for a NOR SR latch, and why? S=1 and R=1 together; it forces both outputs to 0 (not complementary) and leaves the state undecided/metastable on release.
Active-HIGH vs active-LOW — which is NOR, which is NAND? NOR inputs are active-HIGH (1 triggers); NAND inputs are active-LOW (0 triggers).
What do Q p r e v Q n e x t The stored value just before and just after applying new inputs; Hold means Q n e x t = Q p r e v
What is metastability and why does it make the "both active" input forbidden? An unstable balanced state between 0 and 1 that resolves randomly; the forbidden input can trigger it.
