SR latch operation: Exercises — Hardware deep dive

Notation you must have before the exercises

This whole page is written in Boolean algebra: a tiny language for wires that carry only two values, $0$ (LOW, "off", no voltage) and $1$ (HIGH, "on", voltage present). Three operations combine those wires. Read them off the picture below.

How to read this figure: each little block is a truth table. The left block (green, NOT) has one input column $X$ and one output column: flip $0 \to 1$ and $1 \to 0$ . The middle block (AND) lists all four $(X, Y)$ rows and shades the output orange only in the bottom row $(1, 1)$ — the sole case where AND is $1$ . The right block (OR) shades the output orange in every row except the top $(0, 0)$ — OR is $1$ whenever at least one input is on. The bottom caption reminds you that $1 + 1 = 1$ in OR, not $2$ .

Now the two gate rules, which are just NOR $= \overline{X + Y}$ and NAND $= \overline{X \cdot Y}$ read out loud:

Finally, the actual circuit these exercises test. It is two gates whose outputs loop back into each other — that loop is the whole trick.

How to read this figure: the two blue boxes are the NOR gates, G1 (top, output $Q$ in blue) and G2 (bottom, output $\overline{Q}$ in orange). The external input $R$ (red) enters G1; the external input $S$ (green) enters G2. The two dashed lines are the feedback: the blue dashed line carries $Q$ back down into G2's second input, and the orange dashed line carries $\overline{Q}$ back up into G1's second input. That criss-cross is why the circuit is called cross-coupled and why it can hold a value.

Deriving the characteristic equation (the "why", not just the formula)

We want a single formula for $Q_{n e x t}$ from $S$ , $R$ , and $Q_{p r e v}$ , covering only the three legal rows. Build it from what each legal row demands, and watch the waveform picture as we go:

How to read this figure: time runs left to right, split into five labelled segments (Set, Hold, Reset, Hold, Set). Three stacked traces show, from top to bottom, $S$ (green), $R$ (red), and $Q$ (blue); a trace sitting high means $1$ , low means $0$ . Watch the blue $Q$ trace: it rises to $1$ during Set and — crucially — stays at $1$ through the following Hold segment even though both $S$ and $R$ are $0$ there (the blue arrow marks this "held with no input"). It only falls at Reset, then again stays low through the next Hold. That flatness during Hold is the stored bit.

Set row ( $S = 1, R = 0$ ) needs $Q_{n e x t} = 1$ . The cheapest way to force a $1$ into an OR-expression is to add the term $S$ : whenever $S = 1$ , $S + \dots = 1$ . So the formula begins with $S + \dots$
Hold row ( $S = 0, R = 0$ ) needs $Q_{n e x t} = Q_{p r e v}$ — keep the old value. So the " $\dots$ " must reproduce $Q_{p r e v}$ when we are not resetting.
Reset row ( $S = 0, R = 1$ ) needs $Q_{n e x t} = 0$ — the old value must be erased exactly when $R = 1$ . The switch "let $Q_{p r e v}$ through, but kill it when $R = 1$ " is precisely $\overline{R} \cdot Q_{p r e v}$ : it equals $Q_{p r e v}$ when $R = 0$ (since $\overline{R} = 1$ ), and equals $0$ when $R = 1$ (since $\overline{R} = 0$ ).

Gluing the pieces: $Q_{n e x t} = S + \overline{R} Q_{p r e v}, valid only when S \cdot R = 0.$ The side-condition $S \cdot R = 0$ is the promise never to press Set and Reset together — outside it the single-wire model breaks (you will prove this in Problem 5.2).

Level 1 — Recognition

Problem 1.1

For a NOR-based SR latch (active-HIGH), state $Q_{n e x t}$ for all four input combinations $(S, R)$ .

Recall Solution 1.1

Apply the NOR rule directly.

$(0, 0)$ → Hold: $Q_{n e x t} = Q_{p r e v}$ (both gates reproduce the old state).
$(0, 1)$ → Reset: $Q_{n e x t} = 0$ ( $R = 1$ forces $Q = 0$ ).
$(1, 0)$ → Set: $Q_{n e x t} = 1$ ( $S = 1$ forces $\overline{Q} = 0$ , releasing $Q = 1$ ).
$(1, 1)$ → Forbidden: $Q = \overline{Q} = 0$ , not complementary.

Problem 1.2

For a NAND-based SR latch (active-LOW inputs $\overline{S}, \overline{R}$ ), which single input combination is the Hold state, and which is forbidden?

Recall Solution 1.2

Reason from the NAND rule (a $0$ is the active value):

Hold is $\overline{S} = 1, \overline{R} = 1$ (no input active → do nothing).
Forbidden is $\overline{S} = 0, \overline{R} = 0$ (both active → both outputs forced to $1$ , so $Q = \overline{Q} = 1$ , not complementary).

This is the logical dual of NOR: swap the role of $0$ and $1$ on the inputs. See NAND gate.

Level 2 — Application

Problem 2.1

A NOR latch starts at $Q = 0$ . Apply this input sequence (each step: $S$ then $R$ ). Fill in $Q$ after every step.

step	S	R
0	1	0
1	0	0
2	0	1
3	0	0
4	1	0

Recall Solution 2.1

Track the state; Hold keeps whatever was last.

Step 0: $(1, 0)$ Set → $Q = 1$ .
Step 1: $(0, 0)$ Hold → $Q = 1$ (stays 1 — the memory).
Step 2: $(0, 1)$ Reset → $Q = 0$ .
Step 3: $(0, 0)$ Hold → $Q = 0$ .
Step 4: $(1, 0)$ Set → $Q = 1$ .

Answer sequence: $Q = 1, 1, 0, 0, 1$ . Notice steps 1 and 3: no input active, yet $Q$ is definite. That "sticking" is the stored bit.

Problem 2.2

Using the characteristic equation $Q_{n e x t} = S + \overline{R} Q_{p r e v}$ , compute $Q_{n e x t}$ for $S = 0, R = 0, Q_{p r e v} = 1$ , and separately for $S = 0, R = 1, Q_{p r e v} = 1$ .

Recall Solution 2.2

Plug in ( $\overline{R}$ means "NOT $R$ ").

$S = 0, R = 0, Q_{p r e v} = 1$ : $Q_{n e x t} = 0 + \overline{0} \cdot 1 = 0 + 1 \cdot 1 = 1$ . (Hold ✓)
$S = 0, R = 1, Q_{p r e v} = 1$ : $Q_{n e x t} = 0 + \overline{1} \cdot 1 = 0 + 0 \cdot 1 = 0$ . (Reset ✓)

The equation matches the truth table — as it must, since we built it from those rows.

Level 3 — Analysis

Problem 3.1

A NOR latch receives $S = 1, R = 1$ , then both inputs drop to $0$ at the same instant. Gate G1 (producing $Q$ ) has a propagation delay of $3 ns$ ; gate G2 (producing $\overline{Q}$ ) has $5 ns$ . Which output goes HIGH first, and what final stable state results?

Recall Solution 3.1

Under $S = R = 1$ both outputs are $0$ . When both inputs fall to $0$ , each gate now sees both its inputs at $0$ and wants to output $1$ . The waveform below traces the race:

How to read the figure: time in nanoseconds runs left to right; the dashed vertical line at $t = 0$ marks both inputs dropping to $0, 0$ . The blue trace is $Q$ (gate G1): because G1 is faster ( $3 ns$ ), $Q$ rises to $1$ at $t = 3$ (blue arrow, " $Q$ reaches 1 first"). The orange trace is $\overline{Q}$ (gate G2, $5 ns$ ): its dotted portion is the rise it attempted, but the red arrow marks the instant $Q = 1$ feeds back into G2 and pins $\overline{Q}$ to $0$ before it ever finishes rising.

Result: the faster gate wins → $Q = 1, \overline{Q} = 0$ (the Set state).

Key insight: the logic table gave no answer here — only the physical delays decided. In a real chip the delays are not cleanly $3$ vs $5$ ; they can be nearly equal, and then the loop can hover between states → Metastability (Problem 5.3). That unpredictability is why $S = R = 1$ is forbidden.

Problem 3.2

Show why $Q = \overline{Q} = 0$ during $S = R = 1$ cannot be a "stable stored value" the way Hold is.

Recall Solution 3.2

A stable state must re-assert itself with the current inputs. Check self-consistency while $S = R = 1$ :

$Q = \overline{R + \overline{Q}} = \overline{1 + 0} = \overline{1} = 0$ ✓
$\overline{Q} = \overline{S + Q} = \overline{1 + 0} = \overline{1} = 0$ ✓

So $0, 0$ is self-consistent as long as the inputs stay $1, 1$ . The problem is it is not a storable state: the moment you release to Hold ( $S = R = 0$ ) both gates simultaneously try to rise and the outcome depends on delays (Problem 3.1). A genuine memory state ( $Q = 1, \overline{Q} = 0$ or $0, 1$ ) survives the release deterministically; $0, 0$ does not.

Problem 3.3

Now the inputs do not drop simultaneously: from $S = R = 1$ , suppose $R$ falls to $0$ first, and $S$ stays at $1$ a little longer before also falling. What state does the latch land in, and is it predictable this time?

Recall Solution 3.3

While $R$ has already fallen to $0$ but $S$ is still $1$ , the inputs are momentarily $(S, R) = (1, 0)$ — that is the ordinary Set command. So the latch is deterministically driven to $Q = 1, \overline{Q} = 0$ before $S$ falls. When $S$ then drops to $0$ , the inputs become $(0, 0)$ = Hold, which simply keeps $Q = 1$ .

Answer: $Q = 1$ (Set), and it is predictable — because the inputs passed through a legal command $(1, 0)$ on the way down.

General rule: the danger is only the perfectly simultaneous release. Whichever input lingers HIGH last acts as the deciding command: $R$ last → Reset ( $Q = 0$ ); $S$ last → Set ( $Q = 1$ ). Metastability is the knife-edge case where neither lingers measurably longer.

Level 4 — Synthesis

Problem 4.1

Design a small circuit that makes the forbidden state impossible by guaranteeing $R = \overline{S}$ . First prove that a NOR gate with both inputs tied together acts as an inverter; then give the resulting truth table in terms of the single input $S$ , and name the well-known latch you have built. Also state what happens to the Hold and forbidden rows.

Recall Solution 4.1

Step A — NOR as an inverter. Tie both inputs of a NOR gate to the same wire $X$ . The NOR output is $\overline{X + X}$ . But $X + X = X$ (OR-ing a value with itself changes nothing — "at least one is on" is the same as " $X$ is on"). So the output is $\overline{X + X} = \overline{X}$ . A NOR with tied inputs computes NOT. (Check: $X = 0 \Rightarrow \overline{0 + 0} = 1$ ; $X = 1 \Rightarrow \overline{1 + 1} = 0$ — genuine inversion.)

Step B — use it. Feed the latch $R = \overline{S}$ through that inverter. Now $S$ and $R$ can never both be $1$ : if $S = 1$ then $R = 0$ ; if $S = 0$ then $R = 1$ .

$S$	$R = \overline{S}$	action	$Q_{n e x t}$
0	1	Reset	0
1	0	Set	1

So $Q_{n e x t} = S$ directly — the output simply follows the data input. This is the D latch (with the enable held active). The forbidden and Hold rows have both been eliminated by construction.

What happened to the missing rows — the important design consequence. The full SR latch has four input rows; wiring $R = \overline{S}$ makes only two of them reachable ( $S, R = 1, 0$ and $0, 1$ ). The two that vanish are:

Forbidden ( $S = R = 1$ ) — deliberately removed. This is the whole point of the design: the dangerous state is now physically impossible, so no metastability from that source. Pure win.
Hold ( $S = R = 0$ ) — removed as a side-effect, and this is a trade-off, not a free lunch: with the raw inverter you have lost the ability to store. The output slavishly copies $S$ at every instant, so if $S$ glitches, $Q$ glitches. To get memory back you must add an enable line $E$ (Problem 4.2): when $E = 0$ the circuit ignores $S$ and holds. The full D latch is exactly "inverter-fed SR plus an enable" — the enable restores the Hold row that this bare version threw away.

Problem 4.2

Add an enable line $E$ to a NOR SR latch so that $S, R$ only affect the latch when $E = 1$ , and the latch holds when $E = 0$ . Give the gated input equations.

Recall Solution 4.2

Put an AND gate on each control input, gated by $E$ : $S^{'} = S \cdot E, R^{'} = R \cdot E$ feed $S^{'}, R^{'}$ into the SR latch.

When $E = 0$ : $S^{'} = R^{'} = 0$ → the latch sees Hold → stores its bit.
When $E = 1$ : $S^{'} = S, R^{'} = R$ → normal SR behavior.

This is the Gated SR latch. It is the standard first step toward clocked storage and the JK flip-flop.

Level 5 — Mastery

Problem 5.1

A NAND latch has active-LOW inputs $\overline{S}, \overline{R}$ . Both are driven to $0$ (the forbidden state), then released to $1, 1$ (Hold). Explain, using the NAND rule, why the outcome is unpredictable, and relate it to the difference between a latch and a flip-flop.

Recall Solution 5.1

Forbidden state ( $\overline{S} = \overline{R} = 0$ ). Each NAND has a $0$ input, so by the NAND rule (any $0$ input forces output $1$ ) both outputs are forced to $1$ → $Q = \overline{Q} = 1$ . They are no longer complementary — this is the exact dual of the NOR forbidden state where both were $0$ .

The release to $\overline{S} = \overline{R} = 1$ (Hold). Now each NAND sees inputs $(1, other output)$ . Since the other output is currently $1$ , each gate sees $(1, 1)$ → both inputs $1$ → each wants to fall to $0$ . Both gates race downward. By the first-mover rule (Problem 3.1), whichever gate is physically faster falls to $0$ first, feeds that $0$ back into the other gate, and pins the other output at $1$ . The result is a valid complementary state ( $Q, \overline{Q} = 0, 1$ or $1, 0$ ) — but which one depends entirely on the gate delays, not on the logic. With near-equal delays it can even hover halfway → Metastability. That is the unpredictability.

Relation to flip-flop vs latch. A plain latch is level-sensitive: it reacts to its inputs (and enable) at every instant they are active, so a stray forbidden pulse can corrupt it at any moment, and its release can trigger the race above. A flip-flop is edge-triggered: it samples inputs only at a clock edge, shrinking the vulnerable window to that edge. Better still, the JK flip-flop redefines the troublesome "both active" combination as a deterministic toggle ( $Q_{n e x t} = \overline{Q_{p r e v}}$ ) instead of leaving it forbidden — so the metastable-on-release hazard is designed out entirely rather than merely avoided by promise.

Problem 5.2

Prove that the NOR characteristic equation $Q_{n e x t} = S + \overline{R} Q_{p r e v}$ is only valid under $S R = 0$ , by showing what it predicts for $S = R = 1$ and why that prediction is a lie.

Recall Solution 5.2

Substitute $S = 1, R = 1$ into the equation: $\overline{R} = \overline{1} = 0$ , so $Q_{n e x t} = 1 + 0 \cdot Q_{p r e v} = 1 + 0 = 1.$ The algebra cleanly claims $Q_{n e x t} = 1$ . But the real circuit gives $Q = \overline{Q} = 0$ during $S = R = 1$ (verify with the gate equations: $Q = \overline{1 + \overline{Q}} = 0$ and $\overline{Q} = \overline{1 + Q} = 0$ ), and an indeterminate state upon release.

So the single-variable formula succeeds numerically while the hardware does something completely different — the model has no way to represent a state where $Q$ and $\overline{Q}$ are both $0$ , because it only tracks one variable $Q$ . That mismatch is precisely why we bolt on the side-condition $S R = 0$ : it fences off exactly the region where the equation stops describing reality. An equation is only trustworthy inside its stated domain.

Problem 5.3

Sketch what "metastability" actually looks like on the $Q$ wire when the release is on the knife-edge, and explain why $Q$ is neither a clean $0$ nor a clean $1$ for a while.

Recall Solution 5.3

When both gates start rising (or falling) at almost exactly the same time, neither can immediately pin the other. The loop balances near a halfway analog voltage — not a valid $0$ , not a valid $1$ — and lingers there until random circuit noise finally tips it. The figure shows this:

How to read the figure: time runs left to right; the dashed line marks the knife-edge release. The shaded gray band in the middle is the forbidden voltage region — voltages that are neither a logic $0$ nor a logic $1$ . The orange trace shows $Q$ entering that band and hovering there (the flat middle portion) before finally resolving upward to a clean $1$ much later than a normal gate delay.

Why it happens: the two feedback pushes momentarily cancel, exactly like a pencil balanced on its tip — perfectly balanced in theory, but any infinitesimal imbalance eventually wins. Which way and how long it takes are set by microscopic noise, not by the logic, so the settling time is unbounded in the worst case. This is why real designs wait a guaranteed settling time before sampling the output — see Metastability.