SR latch operation: Visual walkthrough — Hardware deep dive

We use the NOR version throughout (the NAND version is its mirror — see the end).

Step 1 — The one rule we need: what a NOR gate does

WHAT. A NOR gate takes two inputs (each a $0$ or a $1$ ) and produces one output. Its rule, stated in plain words:

Why phrase it that way? Because in a latch we constantly ask "is this gate being forced?" — and a single $1$ on either input is enough to force the output to $0$ . That "one $1$ dominates" behaviour is the lever the whole circuit pulls.

WHY this gate. We could use NAND instead (we will, at the end). NOR is chosen first because its active input is a $1$ — matching the everyday intuition "press $1$ to do something."

PICTURE. The four possible input pairs and the single output each produces. Notice the amber row — the only row that outputs $1$ .

Symbol by symbol, the NOR expression $Y = \overline{A + B}$ reads:

$A, B$ — the two inputs (each $0$ or $1$ ).
$A + B$ — logical OR: this is $1$ if at least one input is $1$ .
the overbar $\overline{\cdot}$ — NOT: it flips $1 \leftrightarrow 0$ .
So $Y = \overline{A + B}$ = "flip the OR" = $1$ only when the OR was $0$ = only when both inputs are $0$ . ✓

Step 2 — A lone gate has no memory

WHAT. Take one NOR gate. Drive its inputs, then remove them (set them back to $0$ ). Watch the output.

WHY. We must first prove the problem exists — that a plain gate forgets — so the fix in Step 3 feels necessary, not arbitrary. A gate whose output depends only on the present inputs is called combinational.

PICTURE. Time flows left to right. When the input pulse ends, the output collapses back instantly. Nothing is remembered.

The lesson: to remember, the output at "later" must somehow know what the output was "before." A lone gate has no wire carrying that history. We need to build one.

Step 3 — Cross-couple two gates: the feedback loop is born

WHAT. Take two NOR gates. Feed each gate's output into one input of the other gate. This is cross-coupling.

WHY. This closes a loop. Now a gate's output travels around and comes back as an input — so the circuit's future depends on its own present. That loop is the wire carrying history that Step 2 was missing.

PICTURE. Two NOR gates. The top gate produces $Q$ ; the bottom produces $\overline{Q}$ . The blue feedback wires are the whole trick — trace them with your finger.

Reading the wiring off the picture gives the two governing equations:

$Q = \overline{R + \overline{Q}} \overline{Q} = \overline{S + Q}$

Term by term for the top equation $Q = \overline{R + \overline{Q}}$ :

$R$ — the Reset input feeding the top gate.
$\overline{Q}$ — the other gate's output, fed back in (the blue loop wire).
$R + \overline{Q}$ — the OR of those two; either being $1$ forces the gate.
overbar — NOT, giving the final $Q$ .

The bottom equation $\overline{Q} = \overline{S + Q}$ is the exact mirror: it takes Set $S$ and the fed-back $Q$ .

Step 4 — Hold ( $S = 0, R = 0$ ): the state that keeps itself

WHAT. Set both inputs to $0$ and check whether an assumed state survives.

WHY. This is the memory case. If, with no active input, the equations reproduce the current output, then the output "holds itself up" forever — exactly like the two kids leaning on a rope.

PICTURE. We test the guess $Q = 1, \overline{Q} = 0$ . Follow the arrows: each output, sent around the loop, feeds back and regenerates itself.

Q = \overline{R + \overline{Q}} = \overline{0 + 0} = \overline{0} = 1 ✓ \overline{Q} = \overline{S + Q} = \overline{0 + 1} = \overline{1} = 0 ✓

Top: $R = 0$ and $\overline{Q} = 0$ , so the OR is $0$ , so $Q = \overline{0} = 1$ . The guessed $Q = 1$ came back out — consistent.
Bottom: $S = 0$ and $Q = 1$ , so the OR is $1$ , so $\overline{Q} = \overline{1} = 0$ . The guessed $\overline{Q} = 0$ came back out — consistent.

Both equations returned the values we fed in $\Rightarrow$ self-consistent $\Rightarrow$ stable. The identical check works for $Q = 0, \overline{Q} = 1$ . So $S = R = 0$ means hold the previous bit.

Step 5 — Set ( $S = 1, R = 0$ ): forcing $Q$ to 1

WHAT. Raise $S$ to $1$ , keep $R = 0$ , and follow the forcing.

WHY. This shows how a single $1$ dominates a NOR gate (Step 1's lever) and how that force propagates around the loop to a new stable state.

PICTURE. The amber $S = 1$ slams the bottom gate's output to $0$ ; that $0$ then releases the top gate to rise to $1$ . Two dominoes, in order.

\overline{Q} = \overline{S + Q} = \overline{1 + anything} = \overline{1} = 0 \Rightarrow Q = \overline{R + \overline{Q}} = \overline{0 + 0} = 1

The $S = 1$ makes the OR $= 1$ regardless of $Q$ — that's why we wrote "anything." So $\overline{Q}$ is forced to $0$ first.
Now the top gate sees $R = 0$ and the freshly-made $\overline{Q} = 0$ : OR $= 0$ , so $Q = 1$ .

Result: == $Q = 1$ == (Set). Note the outcome does not depend on what $Q$ was before — Set overwrites.

Step 6 — Reset ( $S = 0, R = 1$ ): the mirror image

WHAT. Raise $R$ to $1$ , keep $S = 0$ .

WHY. By the symmetry of the cross-coupling, Reset is Set with the roles of the two gates swapped. Seeing the mirror confirms we truly understand the mechanism, not just one case.

PICTURE. Now the amber $R = 1$ forces the top gate's $Q$ to $0$ first; that $0$ releases the bottom gate so $\overline{Q} = 1$ .

Q = \overline{R + \overline{Q}} = \overline{1 + anything} = 0 \Rightarrow \overline{Q} = \overline{S + Q} = \overline{0 + 0} = 1

$R = 1$ forces the top OR to $1$ , so $Q = 0$ whatever it was.
Then the bottom gate sees $S = 0$ and $Q = 0$ : OR $= 0$ , so $\overline{Q} = 1$ .

Result: == $Q = 0$ == (Reset).

Step 7 — The degenerate case: Forbidden ( $S = 1, R = 1$ )

WHAT. Drive both inputs to $1$ at once, then examine what happens when they later drop.

WHY. This is the case the parent warned about. It is not a "hold" or a normal state — it breaks the very promise the outputs make (that they are opposites), and its exit is a coin-flip. Every complete truth table must cover it.

PICTURE (part A). Both $1$ s dominate both gates simultaneously, so both outputs go to $0$ — $Q$ and $\overline{Q}$ are now equal, contradicting their names.

Q = \overline{1 + \dots} = 0 and \overline{Q} = \overline{1 + \dots} = 0

PICTURE (part B). Now release both inputs to $0$ at the same instant. Both gates were outputting $0$ , so both now try to rise to $1$ together. Whichever gate is a hair faster (gate delay) wins and pulls the loop to its side. The logic cannot predict the winner — this is metastability.

The symbol $Δ t$ on the figure marks the tiny delay difference between the two gates.
The two amber "?" arrows show both possible landing states — the circuit picks one at random.

Hence $S = R = 1$ is forbidden. The practical cure is to build a circuit where $S$ and $R$ can never both be $1$ — that is exactly what a Gated SR latch and then a D latch do (they generate $R = \overline{S}$ ).

Step 8 — Bundling the four cases into one equation

WHAT. Collapse the three legal rows (Set, Reset, Hold) into a single formula for the next value $Q_{n e x t}$ .

WHY. A formula is a compressed picture of the truth table — it lets a JK flip-flop or D latch designer reason algebraically instead of drawing gates.

The three legal rows say:

S = 1, R = 0 \Rightarrow Q_{n e x t} = 1; S = 0, R = 1 \Rightarrow Q_{n e x t} = 0; S = 0, R = 0 \Rightarrow Q_{n e x t} = Q_{p r e v}

Read as English: "be $1$ if Set; otherwise keep the old value, as long as you're not being Reset." That is:

$Q_{n e x t} = S + \overline{R} Q_{p r e v} valid when S \cdot R = 0$

Term by term:

$S$ — if Set is $1$ , the whole OR is $1$ , so $Q_{n e x t} = 1$ . Set wins outright.
$\overline{R}$ — "not being Reset." It is $1$ when $R = 0$ .
$\overline{R} Q_{p r e v}$ — keep the old bit only if we are not Reset; if $R = 1$ this term is $0$ , clearing the memory.
$S \cdot R = 0$ — the promise never to press both buttons (excludes the forbidden row).

The one-picture summary

This single diagram compresses all seven cases: the loop structure (Step 3), and a mini state-map showing how Set / Reset / Hold move the latch between its two stable states, with the forbidden input pointing into the metastable "no-man's-land."

Recall Feynman: the whole walkthrough in plain words

One gate is a goldfish — it forgets the instant you stop poking it (Steps 1–2). So we wire two gates mouth-to-tail in a little ring, each one holding the other up (Step 3). Now the ring can lean two ways and stays leaning by itself — that's a remembered bit (Step 4, Hold). Push the S button and a single " $1$ " bulldozes one gate down, which lets the other pop up — the ring leans to " $Q = 1$ " (Step 5, Set). Push R and the exact mirror happens — the ring leans the other way to " $Q = 0$ " (Step 6, Reset). Push both buttons and both gates get flattened to $0$ ; when you let go they both scramble up at once and whoever's faster wins — a coin-flip you're forbidden to gamble on (Step 7). Finally we write the ring's behaviour as one tidy sentence, $Q_{n e x t} = S + \overline{R} Q_{p r e v}$ : be $1$ if Set, else keep what you had unless Reset (Step 8).

See also: Flip-flop vs latch · Cross-coupled gates · Gated SR latch · Metastability