3.4.1 · D5Sequential Circuits
Question bank — SR latch operation
First — pin down the vocabulary these traps hinge on
Before any question can trap you, you have to know exactly what each symbol is. Look at the schematic below: two gates, each output fed back into the other. That loop is the whole story.
Where the characteristic equation comes from
The traps below keep referencing . It is not handed down — it is read off the three legal rows of the truth table. Follow the figure:
The NOR ↔ NAND duality, side by side
Verbally saying "roles of 0 and 1 swap" is slippery; the paired tables below make it concrete. Same four behaviours, mirror-image input codes.
True or false — justify
Every item is a claim. Decide true/false, then state why from the NOR/NAND rules before revealing.
A NOR-based SR latch can store a bit even when both inputs are 0.
True — with the Hold rule reproduces whatever already was, so the loop keeps re-asserting its own state. That self-consistency is the memory.
For a NAND-based latch, inputs is the forbidden state.
False — for NAND, is Hold. The forbidden combo is , because that forces both outputs to 1 (not complementary).
and are guaranteed to be opposite for every input combination.
False — the complement guarantee holds only for the three legal inputs. In the forbidden state (NOR ) both outputs are 0 simultaneously, genuinely not complementary.
The "forbidden" input is always the combination where both inputs are 1.
False — "both inputs 1" is forbidden only for the NOR latch. The real definition is "the combo that drives both outputs equal," which for NAND is .
A latch is a combinational circuit like an AND gate.
False — a latch has feedback (outputs wired back to inputs), which a combinational circuit lacks. That loop is exactly what lets it remember after inputs vanish.
In a NOR latch, driving forces directly, regardless of the current .
True — a NOR gate outputs 0 if any input is 1. Since feeds the gate, pins immediately; then is released to become 1.
The NOR and NAND SR latches behave completely differently.
False — they are logical duals: identical Set/Reset/Hold/Forbidden behaviour with the roles of 0 and 1 on the inputs swapped (active-HIGH vs active-LOW).
If you never assert Set and Reset together, the characteristic equation fully describes the latch.
True — that equation is derived precisely under the constraint , which encodes the promise never to press both at once.
Spot the error
Each line contains a flawed statement. Find the specific wrong step and correct it.
" clears the output to 0 because both control lines are off."
Wrong — means "do nothing," so stays whatever it was (0 or 1). Off inputs mean Hold, not clear.
"To Reset a NOR latch, I set ."
Wrong — for an active-HIGH NOR latch, Reset needs (with ). is the inactive value.
"In the forbidden NOR state both outputs go HIGH, so it's ambiguous."
Wrong — in the NOR forbidden state both outputs go LOW (0), not high. The ambiguity appears when the inputs then drop together and both gates race to go high.
"Since a NAND gate's forbidden output is 0, feed it to trigger the hazard."
Wrong — is Hold. NAND's hazard is at , which forces both outputs to 1.
"The characteristic equation is and it works even when ."
Wrong — it is only valid under . At it would predict , but the real hardware gives both outputs 0 and then an unpredictable settle.
"A latch remembers because the wires store charge like a tiny battery."
Wrong — an SR latch remembers through logical feedback: each gate keeps re-driving the other's input to a consistent value. It's a stable loop, not stored charge.
Why questions
Answer with the mechanism, not the label.
Why does the Hold state () preserve the bit rather than reset it?
Because with both inputs 0, each NOR equation reproduces the current outputs ( etc.), so the assumed state is self-consistent and re-asserts itself indefinitely.
Why is asserting both Set and Reset called "forbidden" rather than just "another state"?
Because it breaks the naming contract ( and stop being complements) and, on release, the exit state depends on unequal gate delays — a genuinely unpredictable/metastable outcome.
Why are NAND-latch inputs called active-LOW?
A NAND gate outputs 1 whenever any input is 0, so a 0 on an input is what forces action. Hence 0 is the "active" value — active-LOW.
Why does the characteristic equation use rather than on the term?
Because that term must survive during Hold and vanish during Reset. is 1 when (keep the bit) and 0 when (kill the bit) — exactly the gating we need.
Why does adding logic that makes eliminate the forbidden state?
If is always the opposite of , then and can never both be 1 (or both 0), so the illegal combination can never be applied — the basis of the D latch.
Why does a single logic gate lose its output the moment inputs go away, while a latch does not?
A single gate is combinational — output is a pure function of present inputs, with no path back. A latch routes outputs back into inputs, so a settled state feeds itself and persists.
Why does forcing one output in a NOR latch automatically settle the other?
The two gates are cross-coupled: pinning one output (say via ) removes the only 1 from the other gate's inputs, releasing it to go high — the loop resolves in one propagation.
Edge cases
The boundary situations the topic invites — reason each one out.
At power-up with , what is ?
Indeterminate — Hold preserves the previous value, but at power-up there is no previous value. It settles to 0 or 1 based on gate mismatch until a Set or Reset defines it.
You apply the forbidden , then drop only to 0 (keeping ). What happens?
This is a clean transition into Reset (), so deterministically. The danger is only when both drop together, not one at a time.
Two cross-coupled gates settle into a half-way, non-0/non-1 voltage after the forbidden input. What is this called?
Metastability — an unstable balance point where the loop hovers between valid logic levels before eventually (and unpredictably) resolving to 0 or 1.
Is a bare SR latch level-sensitive or edge-triggered?
Level-sensitive — it responds continuously to input levels with no clock. Edge-triggering requires clocking, which distinguishes a JK flip-flop from a latch (see Flip-flop vs latch).
In the NOR forbidden state both outputs are 0. Is the "output" therefore reliably 0?
No — that 0 is not a stored bit; it's an illegal transient. As soon as the inputs deassert, the value is unpredictable, so you cannot treat it as a valid Reset.
If a NAND latch sits at Hold () forever, does its output drift or decay?
No — the feedback loop actively re-drives the outputs every propagation cycle, so a valid stored bit holds indefinitely as long as power is applied.
Recall One-line summary to lock in
The forbidden state is defined by "both outputs forced equal," never by a fixed bit-pattern — that single idea kills most SR-latch misconceptions.
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