Worked examples — SR latch operation

This page is a drill. The parent note built the theory; here we run the latch through every kind of situation it can meet — every input combination, every startup condition, both the NOR and NAND versions, a real-world word problem, and an exam-style trap.

Before we start, one reminder of the two gate rules we lean on the whole way (nothing new — just so you never have to scroll):

Recall The only two rules you need

NOR output is $1$ only if BOTH inputs are $0$. Any $1$ on a NOR input forces its output to $0$. NAND output is $0$ only if BOTH inputs are $1$. Any $0$ on a NAND input forces its output to $1$.

And the two wiring equations for the NOR latch, copied from the parent so we can plug into them: $Q=\overline{R+\overline{Q}}\overline{Q}=\overline{S+Q}$

Here $Q$ is the stored bit, $\overline{Q}$ is its complement (the "other" output), $S$ is the Set input, $R$ is the Reset input. The bar $\overline{}$ means "flip $0\leftrightarrow 1$" (NOT). The $+$ inside a bar means OR-then-invert = NOR.

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The scenario matrix

Every question this topic can ask falls into one of these cells. The worked examples below are each tagged with the cell they cover, and together they hit all of them.

Cell	What it tests	Covered by
A — Hold from $Q=1$	memory keeps a stored 1	Ex 1
B — Hold from $Q=0$	memory keeps a stored 0	Ex 1
C — Set action	$S=1,R=0\Rightarrow Q=1$	Ex 2
D — Reset action	$S=0,R=1\Rightarrow Q=0$	Ex 2
E — Forbidden + release	$S=R=1$ then both drop	Ex 3
F — Full timing trace	many steps, watch memory stick	Ex 4
G — Unknown power-up state	degenerate: no defined start	Ex 5
H — NAND (active-LOW) version	dual logic, roles of 0/1 swapped	Ex 6
I — Real-world word problem	button/alarm latch	Ex 7
J — Exam twist / characteristic eq.	plug into $Q_{next}=S+\overline{R}{Q}_{prev}$	Ex 8

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Example 1 — Hold from both starting values (Cells A & B)

Part (a): start at $Q=1,\overline{Q}=0$.

1. Compute $\overline{Q}=\overline{S+Q}=\overline{0+1}=\overline{1}=0$. Why this step? A NOR is forced to $0$ by any $1$ input. Here $Q=1$ is that $1$, so $\overline{Q}$ stays $0$.
2. Compute $Q=\overline{R+\overline{Q}}=\overline{0+0}=\overline{0}=1$. Why this step? Now both of this gate's inputs are $0$, and NOR outputs $1$ only when both inputs are $0$ — so $Q$ stays $1$.

The state we assumed came right back out → it is self-consistent (stable). $Q$ stays $1$.

Part (b): start at $Q=0,\overline{Q}=1$.

1. $Q=\overline{R+\overline{Q}}=\overline{0+1}=0$. (the $1$ from $\overline{Q}$ forces it)
2. $\overline{Q}=\overline{S+Q}=\overline{0+0}=1$. (both inputs $0$ → output $1$)

Again the state re-asserts itself. $Q$ stays $0$.

Verify: In both parts the inputs to each gate reproduced the very outputs we started with. That is the definition of Hold — the same input $(0,0)$ can hold either bit, which is exactly why $S=R=0$ is memory, not "clear to 0."

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Example 2 — Set then Reset (Cells C & D)

Step 1 — Set ($S=1,R=0$):

1. $\overline{Q}=\overline{S+Q}=\overline{1+\text{anything}}=0$. Why this step? We attack the gate that has $S$ on it. A $1$ input forces its NOR output to $0$, regardless of the current $Q$. So $\overline{Q}\to 0$ immediately.
2. $Q=\overline{R+\overline{Q}}=\overline{0+0}=1$. Why this step? With $\overline{Q}$ now $0$ and $R=0$, the other gate sees both inputs $0$ → outputs $1$. So $Q=1$. Set done.

Step 2 — Reset ($S=0,R=1$) from $Q=1$:

1. $Q=\overline{R+\overline{Q}}=\overline{1+\dots }=0$. Why this step? Symmetric: the $R$ gate now has a $1$ input, forcing $Q\to 0$.
2. $\overline{Q}=\overline{S+Q}=\overline{0+0}=1$. Reset done, $Q=0$.

Verify: Set drove $Q$ from $0\to 1$; Reset drove it $1\to 0$. Complementarity held throughout: $(Q,\overline{Q})=(1,0)$ then $(0,1)$. Both are legal, complementary states. ✓

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Example 3 — Forbidden state and the race on release (Cell E)

1. While $S=R=1$: $Q=\overline{1+\dots }=0$ and $\overline{Q}=\overline{1+\dots }=0$. Why this step? Each gate has a forcing $1$, so both outputs are $0$. Now $Q$ and $\overline{Q}$ are equal, not complementary — the names lie. (This alone breaks any circuit reading $\overline{Q}$.)
2. Drop both inputs to $0$ simultaneously. Each gate now sees inputs $(0,0)$ from outside, so each wants to output $1$. Why this step? But they read each other's output too. If both went to $1$, each would then see a $1$ from the other and be forced back to $0$ — a contradiction. The loop cannot rest with both high.
3. Whichever gate's output rises a fraction of a nanosecond earlier feeds a $1$ into the other, pinning the slower one at $0$. The faster gate wins. Why this step? "Faster" depends on manufacturing/temperature noise, not on logic — see the red timing arrows in the figure. So the outcome is unpredictable, and briefly metastable (hovering between).

Verify: There is no logically determined answer — that is the whole point. The lesson: never issue $S=R=1$. In practice a Gated SR latch or D latch enforces $R=\overline{S}$ so this can't happen.

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Example 4 — Full timing trace (Cell F)

Apply the truth table row by row (Set→1, Reset→0, Hold→keep):

step	$S$	$R$	rule	$Q$
start	–	–	power-up	1
1	0	0	Hold	1
2	0	1	Reset	0
3	0	0	Hold	0
4	1	0	Set	1
5	0	0	Hold	1
6	0	0	Hold	1
7	0	1	Reset	0

Why each Hold matters: Steps 1, 3, 5, 6 have no active input, yet $Q$ never drifts — it just repeats the last commanded value. Step 5 and step 6 both hold 1 across two idle cycles: the latch is genuinely storing the Set from step 4.

Verify: Final $Q=0$ (last action was Reset). The sequence of outputs is $1,1,0,0,1,1,1,0$. Every Hold copied its predecessor — memory confirmed. ✓ See figure for the waveform.

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Example 5 — Unknown power-up state (degenerate Cell G)

1. $(0,0)$ is the Hold command: "keep the previous value." Why this step? But at power-up there is no previous value — both $Q=0$ and $Q=1$ are self-consistent (Example 1 proved both are stable under $(0,0)$).
2. So which one wins? Whichever gate's output rises first as power ramps — again a tiny-difference race. Why this step? Same mechanism as the forbidden release: two stable states, no logical tiebreaker, so noise decides.

Verify: $Q$ is indeterminate at power-up. This is why real systems always issue an explicit Set or Reset (a "power-on-reset" pulse) before trusting the stored bit. There is no numeric answer — the honest answer is "unknown until you command it." ✓

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Example 6 — The NAND (active-LOW) version (Cell H)

Recall NAND wiring: $Q=\overline{\overline{S}\cdot \overline{Q}}$ and $\overline{Q}=\overline{\overline{R}\cdot Q}$, and the rule "any $0$ input forces output to $1$."

Part (a): $\overline{S}=0,\overline{R}=1$ — this is Set.

1. $Q=\overline{\overline{S}\cdot \overline{Q}}=\overline{0\cdot \dots }=\overline{0}=1$. Why this step? A NAND with a $0$ input is forced to $1$. The active-LOW $\overline{S}=0$ forces $Q=1$. So the "active" value is $0$, not $1$.
2. $\overline{Q}=\overline{\overline{R}\cdot Q}=\overline{1\cdot 1}=\overline{1}=0$. Consistent: $Q=1$. Set done.

Part (b): $\overline{S}=1,\overline{R}=1$ — this is Hold, NOT forbidden.

1. Both inputs are the inactive $1$. Neither gate is forced by an external $0$; each just reads the other. Why this step? Beginners expect "$11$ = forbidden" (copied from NOR). But for NAND the forbidden case is $\overline{S}=\overline{R}=0$ (both outputs forced to $1$). Here $11$ leaves the loop alone.
2. So $Q$ keeps its value from part (a): $Q=1$.

Verify: Set gave $Q=1$; the following $(1,1)$ held it at $1$. The NAND latch is the logical dual of the NOR latch — same behaviour, 0↔1 swapped on the inputs. See Flip-flop vs latch and Cross-coupled gates. ✓

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Example 7 — Real-world word problem (Cell I)

1. At $t_1$: $S=1,R=0\Rightarrow$ Set $\Rightarrow Q=1$ (alarm ON). Why this step? The momentary door pulse Sets the latch.
2. Between $t_1$ and $t_3$: $S=R=0$ (door closed, no clear) $\Rightarrow$ Hold $\Rightarrow Q$ stays $1$. Why this step? This is the purpose of the latch: a one-instant trigger produces a persistent alarm. Closing the door does not un-trigger it — memory holds the 1.
3. At $t_3$: guard presses clear, $R=1\Rightarrow$ Reset $\Rightarrow Q=0$ (alarm OFF).

Verify: Sequence of $Q$: $0\to 1\text{ (at }{t}_1)\to 1\text{ (held)}\to 0\text{ (at }{t}_3)$. The alarm stays on from $t_1$ to $t_3$ despite no continuous input — exactly what a latch is for. ✓

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Example 8 — Exam twist: use the characteristic equation (Cell J)

The equation reads: "$Q_{next}$ is $1$ if we Set, OR if we're not Resetting and the old value was $1$." Here $\overline{R}$ = NOT $R$, and juxtaposition $\overline{R}{Q}_{prev}$ = AND.

Part (a): $S=0,R=1,Q_{prev}=1$.

1. $\overline{R}=\overline{1}=0$. Why this step? $R=1$ means we ARE resetting, so the "keep old value" term must be killed — and $\overline{R}=0$ zeroes it.
2. $Q_{next}=S+\overline{R}{Q}_{prev}=0+(0)(1)=0+0=0$. Why this step? Both terms are $0$ → $Q_{next}=0$. Matches Reset. ✓

Part (b): $S=0,R=0,Q_{prev}=1$.

1. $\overline{R}=\overline{0}=1$. Why this step? Not resetting → the memory term is allowed to pass the old value through.
2. $Q_{next}=0+(1)(1)=0+1=1$. Why this step? The memory term carries $Q_{prev}=1$ straight to the output. Matches Hold. ✓

Verify: Both answers agree with the truth table (Reset→0, Hold→keep 1). Note the constraint $SR=0$ held in both cases ($0\cdot 1=0$, $0\cdot 0=0$), so the equation is valid. ✓ Related: JK flip-flop removes the $SR=0$ restriction entirely.

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Active recall