JK and T flip-flops

3.4.4 · Hardware › Sequential Circuits

JK ki zaroorat KYUN hai?

KAYA galat hai? Jab $S=R=1$ hota hai, hum circuit se kehte hain ki $Q=1$ AUR $Q=0$ ek saath banao. Ek real gate mein yeh ek race paida karta hai aur ek unpredictable output deta hai. Woh ek akela waste hua row ek design sin hai.

JK ise KAISE fix karta hai? JK $S\to J$, $R\to K$ rename karta hai, aur $J=K=1$ case ko "toggle" ($Q_{next}=\overline{Q}$) ka matlab dene ke liye reroute karta hai. Baaki kuch nahi badalta.

JK ko first principles se derive karna

JK ko SR se banao, internal set/reset ko current state par dependent banake: $S=J\cdot \overline{Q},R=K\cdot Q$

Yeh step KYUN? $S=J\overline{Q}$ ka matlab hai "sirf tab set karne ki koshish karo jab hum abhi $0$ hain" ($\overline{Q}=1$). $R=KQ$ ka matlab hai "sirf tab reset karne ki koshish karo jab hum abhi $1$ hain". Kyunki $Q$ aur $\overline{Q}$ kabhi bhi dono ek saath 1 nahi ho sakte, internal $S$ aur $R$ kabhi bhi dono 1 nahi ho sakte — forbidden combination ab structurally impossible hai. Yahi poora jaadu hai.

Ab SR characteristic equation mein substitute karo. Pehle SR ki derive karo: $Q_{next}=S+\overline{R}Q$

KYUN? $S=1$ force karta hai $Q_{next}=1$. Warna ($S=0$) hum $Q$ rakhte hain jab tak $R=1$ use reset na kar de — isliye $\overline{R}Q$.

$S=J\overline{Q}$, $R=KQ$ substitute karo: $Q_{next}=J\overline{Q}+\overline{(KQ)}Q$

$\overline{KQ}\cdot Q=(\overline{K}+\overline{Q})Q=\overline{K}Q+\overline{Q}Q=\overline{K}Q+0=\overline{K}Q$ simplify karo.

Yeh step KYUN? $\overline{KQ}=\overline{K}+\overline{Q}$ (De Morgan), aur $\overline{Q}Q=0$. Toh:

Khud ko convince karne ke liye charon rows ko boxed formula se check karo — yahi derive karne ka point hai.

T flip-flop = JK jisme $J=K=T$

Iska characteristic equation derive karo JK equation mein $J=K=T$ daalkaar: $Q_{next}=T\overline{Q}+\overline{T}Q$

Yeh step KYUN? Woh expression bilkul XOR ki definition hai.

Iska KYUN matter karta hai: T flip-flops ki ek chain (har ek ko pichle wale ka output feed karke) ek ripple counter hoti hai — har stage pehle wale se aadhi rate par toggle karti hai, jo frequency ko 2, 4, 8, … se divide karta hai.

Excitation tables (circuits design karne ke liye)

Characteristic tables ka jawab hai "given inputs, output kya hai?". Excitation tables iska ulta jawab deti hain — "main yeh transition chahta hoon, mujhe kaunse inputs chahiye?" — jo aap actually counters banate waqt use karte ho.

JK mein don't-cares KYUN? $0\to 1$ jaane ke liye hume set karna hoga, isliye $J=1$; lekin $K$ irrelevant hai kyunki $K$ sirf tab act karta hai jab $Q=1$ ho. Woh freedom (X) hi JK ko K-maps mein implement karna sasta banati hai.

Worked examples

Common mistakes

Flashcards

Connections

• SR Flip-Flop — parent jisse JK derive hota hai
• D Flip-Flop — doosra "no forbidden state" fix ($Q_{next}=D$)
• Edge-Triggering and Master-Slave — KYUN JK race nahi karta
• Ripple Counters — cascaded T flip-flops se bante hain
• Excitation Tables and Sequential Design
• Karnaugh Maps — jahan JK ke don't-cares logic reduce karte hain
• XOR Gate — T flip-flop ka dil

Concept Map