Worked examples — Edge-triggered D flip-flop

Before anything else, one reminder so no symbol appears un-earned:

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The scenario matrix

Think of a table where each row is a distinct kind of situation a problem can throw at you. Every cell must be covered by at least one worked example below.

Cell	Scenario class	What's tricky about it	Covered by
A	Positive-edge waveform read	$D$ wiggles between edges — must be ignored	Ex 1
B	Negative-edge device	Active edge is the falling one — opposite sign	Ex 2
C	Degenerate input: $D$ held constant	No output change ever	Ex 3
D	Feedback: $\overline{Q}\to D$ (toggle)	Output depends on itself → ÷2	Ex 4
E	Timing: setup/hold satisfied	Compute $f_{max}$, verify margin	Ex 5
F	Timing: setup violated (limiting case)	Metastability — the failure boundary	Ex 6
G	Real-world word problem	Turnstile / counter framing	Ex 7
H	Exam twist: asynchronous reset overrides clock	Clear beats the edge	Ex 8
I	Multi-stage shift register	One hop per edge, all stages together	Ex 9

The signs/quadrant analogue here is which clock edge is active (rising vs falling) — cells A and B. The zero/degenerate case is cell C. The limiting behaviour is cell F (the setup boundary where the device breaks). Let's hit them all.

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Ex 1 — Positive-edge waveform read (Cell A)

Forecast: guess the four values of $Q$ after $t=2,4,6,8$ before reading on.

1. At $t=2$ ↑: read $D$. Right at $t=2$, $D=1$ (we're inside the $0$–$3$ window). So $Q\to 1$. Why this step? The law says sample only at the edge. The edge is at $t=2$; nothing before or after matters.
2. Between $t=2$ and $t=4$: $Q$ stays $1$ even though $D$ drops to $0$ at $t=3$. Why? No edge occurs between them, so $Q$ is frozen. The drop at $t=3$ is invisible to $Q$.
3. At $t=4$ ↑: $D=0$ now (we're in the $3$–$5$ window). So $Q\to 0$. Why? Same law — the edge samples the current $D$, which is $0$.
4. At $t=6$ ↑: $D=1$ (in the $5$–$7$ window). So $Q\to 1$. The glitch near $t=6.5$ is after the edge → ignored. Why? The edge already passed; the flap has snapped shut.
5. At $t=8$ ↑: $D=0$ ($t\ge 7$ window). So $Q\to 0$.

Answer: $Q$ after edges $=1,0,1,0$.

Verify: Sanity check — each output equals the value of $D$ at its edge, never a between-edge value. The glitch at $6.5$ changed nothing, exactly as edge-triggering promises. ✓

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Ex 2 — Negative-edge device (Cell B)

Forecast: the active instant is now the falling edge — a different sign of the clock transition. Guess the outputs.

1. At $t=3$ ↓: what is $D$ right at $t=3$? It is the boundary $1\to 0$. Take the value in the window we're entering: for a clean read the device sees the settled value $D=0$. So $Q\to 0$. Why this step? A negative-edge device's active edge is $1\to 0$; we sample $D$ there, not at any rising edge.
2. At $t=5$ ↓: $D=1$ (window $5$–$7$). So $Q\to 1$. Why? Same rule, next falling edge.
3. At $t=7$ ↓: $D=0$. So $Q\to 0$.

Answer: $Q$ after edges $=0,1,0$.

Verify: Contrast with Ex 1 — same waveform, different edge polarity, different captured sequence. This proves the sign of the edge genuinely changes the result, just as quadrant sign changes an angle. ✓

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Ex 3 — Degenerate input: $D$ held constant (Cell C)

Forecast: does $Q$ oscillate, count, or settle?

1. Edge 1: sample $D=1$ → $Q\to 1$. Why? $Q_{n+1}=D=1$.
2. Edge 2: sample $D=1$ again → $Q$ stays $1$. Why? $D$ never changes, so every edge loads the same value.
3. Edges 3–10: identical — $Q=1$ each time.

Answer: $Q=1$ after edge 1, and $Q=1$ after edge 10 (and forever after).

Verify: This is the degenerate / zero-variation case. The characteristic equation $Q_{n+1}=D$ has no dependence on $Q_n$, so a constant $D$ produces a constant $Q$ from edge 1 onward. If your model instead toggled or held the initial $0$, it would be wrong — check against $Q_{n+1}=D$ directly. ✓

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Ex 4 — Feedback toggle (÷2) (Cell D)

Forecast: with the output feeding its own input, what pattern emerges?

1. Before edge 1: $Q=0$, so $\overline{Q}=1$, so $D=1$. Why this step? $D$ is wired to $\overline{Q}$; we must compute $D$ from the current $Q$ before the edge.
2. Edge 1: sample $D=1$ → $Q\to 1$. Now $\overline{Q}=0$, so $D$ becomes $0$. Why? $Q_{n+1}=D=\overline{Q_n}$: the new $Q$ is the opposite of the old one.
3. Edge 2: $D=0$ → $Q\to 0$. Then $D\to 1$.
4. Edge 3: $D=1$ → $Q\to 1$.
5. Edge 4: $Q\to 0$.

Answer: $Q$ after edges $=1,0,1,0$. It takes two clock edges for $Q$ to complete one full $0\to 1\to 0$ cycle, so $Q$'s frequency is half the clock's: $f_Q=f_{CLK}/2$.

Verify: The general rule $Q_{n+1}=\overline{Q_n}$ gives the sequence $0\to 1\to 0\to 1$, period $=2$ edges $=1$ output cycle per $2$ input cycles $\Rightarrow$ divide-by-2. This is the toggle/T-flip-flop behaviour behind Synchronous counters. ✓

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Ex 5 — Timing satisfied: compute $f_{max}$ (Cell E)

Forecast: which numbers add, and which one is a lower constraint not part of the sum?

1. Identify the data-path chain in one period: the edge fires, data leaves the first FF after $t_{cq}$, crosses logic in $t_{comb}$, and must be stable $t_{su}$ before the next edge. Why this step? All three events happen in series along one clock cycle, so their times add.
2. Sum them: $T_{clk}\ge t_{cq}+t_{comb}+t_{su}=3+4+2=9\text{ns}.$ Why? The next edge cannot arrive until the receiving FF's setup is met.
3. Invert to get frequency: $f_{max}=\frac{1}{T_{min}}=\frac{1}{9\text{ns}}=\frac{1}{9\times 10^{-9}\text{s}}\approx 1.11\times 10^8\text{Hz}\approx 111\text{MHz}.$ Why? Frequency is one over period; smaller period ⇒ higher speed.
4. What about $t_h=1$ ns? It does not enter $f_{max}$. Hold time is a constraint on fast paths (data arriving too early), fixed by ensuring $t_{cq}+t_{comb}\ge t_h$: here $3+4=7\ge 1$ ✓, so no hold violation. Why? Hold sets a minimum delay, not a maximum period.

Answer: $T_{min}=9$ ns, $f_{max}\approx 111$ MHz, hold satisfied.

Verify: Units: $\text{ns}\to$ s gives Hz on inversion. $1/(9\times 10^{-9})=1.111\times 10^8$ Hz. ✓ Hold check $7\ge 1$ ✓. See Setup and hold time.

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Ex 6 — Setup violated: the limiting failure case (Cell F)

Forecast: we computed $T_{min}=9$ ns in Ex 5. What does running at $8$ ns do?

1. Compute the data arrival time (relative to the launching edge): $t_{arrive}=t_{cq}+t_{comb}=3+4=7\text{ns}.$ Why this step? This is when valid data reaches the receiving FF's $D$ pin.
2. Compute the required arrival time — data must be stable $t_{su}$ before the next edge at $T_{clk}=8$: $t_{required}=T_{clk}-t_{su}=8-2=6\text{ns}.$ Why? Setup means "settled this long before the edge."
3. Setup slack = required − arrive: $\text{slack}=t_{required}-t_{arrive}=6-7=-1\text{ns}.$ Why? Positive slack = margin to spare; negative slack = data is late.
4. Interpret the negative slack: data changes inside the keep-out window $[t_{su}\text{ before}]$. The FF may enter metastability — $Q$ hovers between 0 and 1 and resolves after an unpredictable delay. Why? This is the limiting boundary of Ex 5: at exactly $T=9$ slack $=0$; below it the device breaks.

Answer: slack $=-1$ ns (violated) → risk of Metastability. Must raise $T_{clk}$ to $\ge 9$ ns.

Verify: At $T=9$: slack $=(9-2)-7=0$, the exact edge of correctness — consistent with $f_{max}$ from Ex 5. At $T=8$: slack $=-1<0$ ✓ violation. The sign of the slack is the whole story. ✓

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Ex 7 — Real-world word problem (Cell G)

Forecast: the car arrives between edges — which edge notices it?

1. Edge at $t=2$ s: car not yet on pad (arrives $2.4$) → $D=0$ → $Q=0$ (lamp off). Why this step? Sample $D$ at the edge; the car's future arrival is invisible.
2. Edge at $t=3$ s: car is on pad (since $2.4$) → $D=1$ → $Q=1$ (lamp ON). Why? First edge that sees the car.
3. Edge at $t=4$ s: car still on pad (leaves at $4.7$) → $D=1$ → lamp stays on.
4. Edge at $t=5$ s: car left at $4.7$ → $D=0$ → $Q=0$ (lamp OFF).

Answer: lamp turns on at $t=3$ s, off at $t=5$ s.

Verify: The lamp lags the physical car by up to one clock (car arrived $2.4$, lamp on at $3.0$; car left $4.7$, lamp off at $5.0$). This "up to one tick of delay" is exactly the D = Delay behaviour — a sanity check that the model behaves like a sampled system. ✓

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Ex 8 — Exam twist: asynchronous reset overrides the clock (Cell H)

Forecast: the clear pulse happens between edges — but it's asynchronous. Does $Q$ change?

1. At $t=1$ ↑: $\overline{CLR}=1$ (normal), $D=1$ → $Q\to 1$. Why this step? Clear inactive, so ordinary edge behaviour applies.
2. During $t\in [1.5,1.8]$: $\overline{CLR}=0$ → $Q$ forced to $0$ right away, with no edge needed. Why? "Asynchronous" means the clear does not wait for a clock edge — it overrides everything.
3. After $t=1.8$: $\overline{CLR}$ back to $1$; $Q$ stays at $0$ (frozen, no edge yet). Why? Clearing released, but nothing re-loads $Q$ until the next edge.
4. At $t=2$ ↑: $\overline{CLR}=1$, $D=1$ → $Q\to 1$ again.

Answer: $Q$: $0\to 1$ (at $t=1$) $\to 0$ (during clear) $\to 1$ (at $t=2$).

Verify: The key exam trap is step 2: a synchronous clear would wait for $t=2$ and never show the mid-interval drop. Because ours is asynchronous, $Q$ dips to $0$ between edges. The output visited $0$ once more than a naïve edge-only trace predicts — the twist is doing its job. ✓

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Ex 9 — Multi-stage shift register (Cell I)

Forecast: does the first bit reach $Q_3$ in one edge or three?

1. Edge 1 (input $=1$): each FF loads the value that was on its $D$ just before the edge. Before edge 1: $D_1=1$, $D_2=Q_1=0$, $D_3=Q_2=0$. So $(Q_1,Q_2,Q_3)=(1,0,0)$. Why this step? Edge-triggering makes every stage sample the old upstream value simultaneously → one hop per edge, no racing.
2. Edge 2 (input $=0$): before edge: $D_1=0$, $D_2=Q_1=1$, $D_3=Q_2=0$. → $(0,1,0)$. Why? The $1$ from stage 1 moves to stage 2; the new $0$ enters stage 1.
3. Edge 3 (input $=1$): before: $D_1=1$, $D_2=Q_1=0$, $D_3=Q_2=1$. → $(1,0,1)$.
4. Edge 4 (input $=1$): before: $D_1=1$, $D_2=Q_1=1$, $D_3=Q_2=0$. → $(1,1,0)$.

Answer:

After edge	$Q_1$	$Q_2$	$Q_3$
1	1	0	0
2	0	1	0
3	1	0	1
4	1	1	0

Verify: The first input bit ($1$, injected before edge 1) appears at $Q_1$ after edge 1, at $Q_2$ after edge 2, at $Q_3$ after edge 3 — exactly one stage per edge, three edges to traverse three stages. If it had raced to $Q_3$ in a single edge, we'd have transparent-latch behaviour, which the edge forbids (see Registers and shift registers). ✓

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Recall Rapid self-test

Positive vs negative edge — which clock transition is active for each? ::: Positive = rising $0\to 1$; negative = falling $1\to 0$. With $D$ tied to constant 1, what is $Q$ after many edges? ::: 1 (constant), since $Q_{n+1}=D$ is independent of $Q_n$. $\overline{Q}\to D$ produces what output frequency? ::: Half the clock — divide-by-2 toggle. $t_{cq}=3,t_{comb}=4,t_{su}=2$ ns → $f_{max}$? ::: $1/9\text{ns}\approx 111$ MHz. If setup slack is $-1$ ns, what may happen? ::: Metastability — $Q$ hovers between 0 and 1. Asynchronous clear vs synchronous clear — difference? ::: Async forces $Q=0$ immediately (no edge needed); sync waits for the next active edge. In a 3-stage shift register, how many edges for a bit to reach the last stage? ::: Three — one hop per edge.

Connections

• Edge-triggered D flip-flop — the parent (rules these examples apply)
• SR latch · Gated D latch · Master-slave configuration — how the edge is built
• Setup and hold time · Metastability — Ex 5 & Ex 6
• Registers and shift registers — Ex 9
• Synchronous counters · T flip-flop · JK flip-flop — Ex 4 toggle
• Clock distribution and skew — why one shared clock keeps stages in step