Edge-triggered D flip-flop

3.4.3 · Hardware › Sequential Circuits

YEH HAI KYA?

Subscript matter karta hai: $Q_{n + 1}$ woh state hai jo edge ke baad hogi, $D$ se compute ki gayi jo edge par sample ki gayi.

KAISE BANTA HAI? (Scratch se derivation)

Hum ise teen layers mein banate hain, har ek pichli ki flaw solve karta hai.

Layer 1 — SR latch (feedback = memory)

Do NOR gates cross-couple karo:

$Q = \overline{R + \overline{Q}}, \overline{Q} = \overline{S + Q}$

$S = 1, R = 0 \Rightarrow Q = 1$ (Set)
$S = 0, R = 1 \Rightarrow Q = 0$ (Reset)
$S = R = 0 \Rightarrow$ hold (feedback last value rakhta hai) → yahi memory hai.
$S = R = 1 \Rightarrow$ forbidden.

Layer 2 — Gated D latch (forbidden state hatao)

$S$ aur $R$ ko opposites banao aur unhe Enable se gate karo: $S = D \cdot E, R = \overline{D} \cdot E$ Jab $E = 1$ : $S = D, R = \overline{D}$ → $Q = D$ (transparent). Jab $E = 0$ : $S = R = 0$ → hold. Forbidden state kabhi nahi aa sakti kyunki $S, R$ complementary hain. Lekin yeh abhi bhi level-triggered hai.

Layer 3 — Master–slave = edge behaviour

Do D latches ko opposite enables ke saath chain karo:

Master latch $\overline{C L K}$ se enable hota hai
Slave latch $C L K$ se enable hota hai

Rising edge trace karo:

Jab $C L K = 0$ : master transparent hai ( $D$ track karta hai), slave band hai (purana $Q$ hold karta hai).
Rising edge $C L K : 0 \to 1$ par: master us value ko freeze kar leta hai jo edge se just pehle thi; slave khulta hai aur us frozen value ko $Q$ mein copy karta hai.
Jab $C L K = 1$ : master band (naye $D$ ko ignore karta hai), slave transparent hai lekin uska input (master output) frozen hai → $Q$ stable.

Result: $Q$ ek baar, edge par, change hota hai, woh jo bhi $D$ edge se just pehle tha. Yahi exactly edge-triggering hai. 🎉

Formula Characteristic equation & table

$Q_{n + 1} = D$

$D$	$Q_{n}$	$Q_{n + 1}$
0	0	0
0	1	0
1	0	1
1	1	1

Next state $Q_{n}$ par depend nahi karta — D flip-flop simply $D$ ko load karta hai. (Compare karo JK se jahan $Q_{n + 1} = J \overline{Q_{n}} + \overline{K} Q_{n}$ .)

Timing: woh numbers jo ise real banate hain

Worked examples

Flashcards

Edge-triggered aur level-triggered storage mein kya farq hai?

Edge-triggered (flip-flop) output sirf clock edge par update karta hai; level-triggered (latch) poore clock level ke liye transparent hota hai.

D flip-flop ki characteristic equation

Q_{n + 1} = D

(next state = sampled input,

Q_{n}

se independent).

Do latches ko opposite enables ke saath kyun chain karte hain (master–slave)?

Taaki ek waqt mein exactly ek hi khula ho; value edge par freeze ho jaaye, edge-triggered (non-transparent) behaviour milta hai.

Setup time define karo.

Minimum time jitna D ko active clock edge se pehle stable rehna chahiye taaki reliably capture ho sake.

Hold time define karo.

Minimum time jitna D ko edge ke baad stable rehna chahiye.

Metastability kya hai?

Ek unstable state jahan Q 0 aur 1 ke beech hover karta hai, setup/hold violate karne se hota hai; unpredictable delay ke baad resolve hota hai.

FF→logic→FF path ke liye max clock frequency ka formula

f_{ma x} = 1/ (t_{c q} + t_{co mb} + t_{s u})

D flip-flop ko toggle (÷2) kaise banate hain?

\overline{Q}

D

se connect karo; har edge Q ko invert karta hai.

Edge-triggering safe shift registers kyun enable karta hai?

Edge input ko almost instantly band kar deta hai, isliye data clock ki jagah ek stage per clock hop karta hai, race nahi karta.

Positive-edge FF kaunse clock event se trigger hota hai?

Clock ki rising (0→1) transition se.

Recall Feynman: 12-saal ke bachche ko samjhao

Ek mailbox imagine karo jisme ek flap hai jo snap shut hoti hai. Ek postman (clock) har tick mein ek baar guzarta hai. Jis exact moment woh guzarta hai, jo bhi letter (D) tumhare haath mein hai woh box mein chali jaati hai — aur flap slam ho jaati hai. Baaki time box locked rehta hai: tum koi bhi letter hilaate raho, kuch nahi badalta. Jab postman phir aata hai, box teri nayi letter se swap ho jaata hai. Woh "guzarne ke moment par snap" hi edge hai. Isliye poora computer neat rehta hai: sabke mailbox saath, ek tick mein update hote hain.

Connections

SR latch — bistable core (feedback se memory)
Gated D latch — forbidden state hata deta hai, abhi bhi level-triggered
Master-slave configuration — edge kaise achieve hoti hai
JK flip-flop / T flip-flop — richer characteristic equations
Setup and hold time & Metastability — timing correctness
Registers and shift registers — bahut saare D-FFs ek clock share karte hain
Synchronous counters — toggling D/T flip-flops se bante hain
Clock distribution and skew — kyun sabke liye ek edge matter karta hai