Worked examples — Registers and shift registers

Before we start, one picture fixes the vocabulary we will use in every single example.

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The scenario matrix

Every problem this topic can hand you is one of these cells. The examples below are tagged with the cell they cover, and together they hit all of them.

#	Case class	What's tricky about it	Example
A	Left shift, unsigned, no overflow	plain ×2	Ex 1
B	Left shift with overflow (bit falls off MSB)	×2 breaks	Ex 2
C	Right shift, unsigned	floor ÷2, LSB lost	Ex 3
D	Right shift, signed (arithmetic)	sign bit must be copied	Ex 4
E	Serial In $=1$ vs $=0$	entering bit is external	Ex 5
F	SIPO — serial → parallel assembly	LSB-first ordering	Ex 6
G	PISO — parallel → serial transmission	which bit leaves first	Ex 7
H	Degenerate: all-zeros / all-ones input	limiting behaviour	Ex 8
I	Traversal timing (n edges)	counting the delay	Ex 9
J	Real-world + exam twist (ring counter)	feedback wraps the end	Ex 10

Every numeric answer below is machine-checked in the verify block.

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Ex 1 — Left shift, unsigned, no overflow (cell A)

1. Edge 1. Apply $Q_i^{\text{next}}=Q_{i-1}$, with $Q_0^{\text{next}}=\text{Serial In}=0$. So $0010\to 0100$. Why this step? Left shift = every bit slides one place toward the MSB; the vacated LSB is filled by Serial In.
2. Edge 2. Again: $0100\to 1000$. Why this step? Same rule, applied once more.

Verify: $0100_2=4$, $1000_2=8$. Doubling $2\to 4\to 8$. ✔ No bit ever fell off the MSB (the leading bit was $0$ each time), so ×2 held exactly.

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Ex 2 — Left shift with overflow (cell B)

1. Apply the rule. $1010\to 0100$. The old MSB (a $1$, worth $2^3=8$) slid off the left edge and is gone. Why this step? The register has no fifth flip-flop; whatever leaves $Q_3$ is discarded.
2. Read the result. $0100_2=4$, not $20$. Why this step? The lost bit was worth $8$; doubling gives $20=4+16$, and $16$ is exactly the discarded $2^4$ place, leaving $4$.

Verify: $20\mathrm{mod}16=4$. ✔ Left shift is ×2 only modulo $2^n$ — when the MSB is $1$, the answer wraps.

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Ex 3 — Right shift, unsigned (cell C)

1. Edge 1. $Q_i^{\text{next}}=Q_{i+1}$, MSB gets Serial In $=0$: $1011\to 0101$. The old LSB $1$ fell off the right. Why this step? Right shift slides toward the LSB; the vacated MSB is filled by Serial In.
2. Edge 2. $0101\to 0010$. Another $1$ dropped. Why this step? Same rule again.

Verify: $0101_2=5$, $0010_2=2$. Sequence $11\to 5\to 2$. Floor division: $\lfloor 11/2\rfloor =5$, $\lfloor 5/2\rfloor =2$. ✔ Right shift is floor ÷2 because the discarded LSB (the remainder) is thrown away.

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Ex 4 — Right shift, signed (arithmetic) (cell D)

1. Identify the sign bit. MSB $=1$ means negative. In two's complement the value of $1100$ is $-(2^4)+12=-4$. Why this step? We must know the sign to preserve it.
2. Arithmetic shift = copy the sign into the vacated MSB. So Serial In $=$ old MSB $=1$: $1100\to 1110$. Why this step? A logical shift would inject $0$ and flip a negative into a large positive. Copying the sign keeps the number negative.
3. Decode the result. $1110=-(16)+14=-2$. Why this step? Confirms the division worked in the signed world.

Verify: $-4/2=-2$ ✔, and $1110$ as signed 4-bit $=-2$ ✔. Logical shift would have given $0110=+6$ ✔ (the wrong answer we avoided).

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Ex 5 — Serial In = 1 vs 0 (cell E)

1. Edge 1: $0000\to 0001$ (a $1$ enters $Q_0$). Why? Serial In lands in the vacated LSB.
2. Edge 2: $0001\to 0011$. Why? Old bit slides up, new $1$ enters.
3. Edge 3: $0011\to 0111$. Why? Same march.
4. Edge 4: $0111\to 1111$. Why? Register now saturated with ones.

Verify: After 4 edges with Serial In $=1$: $1111_2=15$. With Serial In $=0$ the register would stay $0000=0$ forever (nothing new but zeros enter). ✔ The entering bit is an external line, not part of the chain — leave it undefined and you shift in garbage.

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Ex 6 — SIPO: serial stream → parallel word (cell F)

The figure tracks the word building up clock by clock.

1. Clock 1, Serial In $=1$: $0000\to 0001$. Why? First (LSB) bit lands in $Q_0$.
2. Clock 2, Serial In $=0$: $0001\to 0010$. Why? Earlier bit slides up to $Q_1$; new $0$ enters $Q_0$.
3. Clock 3, Serial In $=1$: $0010\to 0101$. Why? Keep marching.
4. Clock 4, Serial In $=1$: $0101\to 1011$. Why? The last (MSB) bit fills $Q_3$; word complete.

Verify: Final parallel word $=1011$. The first bit received ($1$) sat down at $Q_0$ (the LSB) and the last ($1$) at $Q_3$ — exactly LSB-first packing. ✔

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Ex 7 — PISO: parallel word → serial stream (cell G)

1. Before edge 1: $Q_0=1$ is sent. Then right shift: $1011\to 0101$. Why this step? We output the LSB, then slide everyone toward the LSB.
2. Before edge 2: $Q_0=1$ sent. Shift: $0101\to 0010$. Why this step? Same rule — read the current LSB, then shift once toward the LSB with Serial In $=0$.
3. Before edge 3: $Q_0=0$ sent. Shift: $0010\to 0001$. Why this step? The new LSB is now $0$; we output it, then shift again by the identical rule.
4. Before edge 4: $Q_0=1$ sent. Shift: $0001\to 0000$. Why this step? Last remaining bit is at $Q_0$; output it, and the final shift empties the register.

Verify: Transmitted sequence $=1,1,0,1$ (LSB first). This is the same LSB-first order the Ex 6 SIPO receiver expects, so feeding it back rebuilds $1011$ ✔ — PISO and SIPO are inverses, which is the whole point of serial links.

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Ex 8 — Degenerate inputs: all-zeros and all-ones (cell H)

1. Case (a), starts $0000$: every shift is $0000\to 0000$. Why? Zeros slide into zeros; nothing to move. Fixed point.
2. Case (b), starts $1111$: $1111\to 1110\to 1100\to 1000\to 0000$. Why? Each edge pushes one $1$ off the MSB and pulls a $0$ in at the LSB; after 4 edges (register width) all ones are flushed.

Verify: (a) stays $0000$ ✔. (b) reaches $0000$ after exactly $4$ edges ✔ — a full-width flush, matching the "n edges to traverse" rule of Ex 9.

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Ex 9 — Traversal timing (cell I)

1. Count the stages. SISO chains $n=8$ flip-flops; a bit advances exactly one stage per edge. Why? Each D flip-flop samples its input only at the active edge.
2. Add them up. Entering at edge #1, the bit reaches the last flip-flop's output after $8$ edges — visible at Serial Out on edge #8 (relative to entry it is $n$ edges of delay).

Verify: Delay $=n=8$ edges ✔. This is why a SISO register is literally a "programmable delay" measured in clock ticks.

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Ex 10 — Real-world + exam twist: ring counter (cell J)

1. Edge 1: left shift, but Serial In $=$ old MSB $=0$: $0001\to 0010$. Why? The MSB that "falls off" is fed back to the LSB; here the departing bit was $0$.
2. Edge 2: $0010\to 0100$. Why? The lone $1$ keeps walking up.
3. Edge 3: $0100\to 1000$. Why? $1$ now at the MSB.
4. Edge 4: MSB $1$ falls off and is fed back to the LSB: $1000\to 0001$. Why? Feedback closes the ring — we are back to the start.

Verify: States $0001,0010,0100,1000,0001,\dots$ — period $=4=n$. ✔ A ring counter with one hot bit cycles through exactly $n$ states, a cheap one-hot sequencer built from a shift register plus feedback.

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Active Recall

Recall Which cells break the "shift = ×2 / ÷2" shortcut, and why?

Cell B (left shift with a $1$ leaving the MSB → wraps mod $2^n$) and cell D (signed right shift needs the sign bit copied, not a $0$). Both fail because a bit crossing the end of a finite register carries real place value.

Connections

• D flip-flop — the one-edge delay behind every example's timing.
• Multiplexers — selects shift-direction / load in a real chip.
• Counters — Ex 10's ring counter is a shift register with feedback.
• Serial communication (UART, SPI) — Ex 6 (SIPO receive) & Ex 7 (PISO transmit).
• Binary multiplication and division — cells A–D are the shift steps of shift-and-add / shift-and-subtract.
• Clocking and setup/hold time — Ex 9's delay is measured in valid clock edges.

Concept Map

The figure below shows how the single shift rule branches into every scenario worked on this page.