Registers and shift registers — Hinglish notes

3.4.7 · Hardware › Sequential Circuits

Ek register bas flip-flops ki ek row hoti hai jo bits ko saath milke yaad rakhti hai. Ek shift register additionally un bits ko har clock pe sideways move karta hai. Neeche jo bhi hai woh sab ek single D flip-flop se build up hota hai.

Starting point: the D flip-flop

1. The Register (parallel load)

HOW yeh kaam karta hai (atom se derivation): $n$ D flip-flops lo. Unke saare clocks ek saath wire karo. Har ek ko apna $D_{i}$ do aur har ek $Q_{i}$ read karo. $Q_{i}^{next} = D_{i} for i = 0, 1, \dots, n - 1$ Edge pe, saare $D_{i} \to Q_{i}$ ek saath → poora word ek clock tick mein capture ho jaata hai.

Load-Enable add karna (kyun control chahiye)

Ek plain register har edge pe $D$ grab karta hai. Aam taur pe hum chahte hain ki woh hold kare jab tak load karne ke liye na kaha jaaye.

Derivation: hum chahte hain $Q^{next} = {D Q if L O A D = 1 if L O A D = 0$ Flip-flop input ko $L O A D$ se fed ek 2-to-1 mux use karke build karo: $D_{ff} = L O A D \cdot D + \overline{L O A D} \cdot Q$ Jab $L O A D = 0$ hota hai, flip-flop apna output khud ko feed back karta hai → woh yaad rakhta hai. Yahi exactly woh tarika hai jis se ek CPU register sirf tab update hota hai jab instruction kehe.

2. The Shift Register

Atom se derivation: flip-flop $i$ ko apna khud ka baahri $D_{i}$ dene ki bajaye, use pichle flip-flop ka output feed karo: $D_{i} = Q_{i - 1}$ . Phir har edge pe pattern ek position slide karta hai; ek naya bit ek end se enter karta hai, aur door wala bit Serial Out ke roop mein bahar nikalta hai.

Chaar classic types (WHAT combinations exist)

Data in serially ya parallel mein ja sakta hai, aur out serially ya parallel mein aa sakta hai:

Type	In	Out	Use
SISO	Serial	Serial	delay line / time buffer
SIPO	Serial	Parallel	serial data receive karo, word ki tarah padho
PISO	Parallel	Serial	ek word ko ek bit at a time transmit karo
PIPO	Parallel	Parallel	yeh bas routing waala register hai

Timing intuition (Forecast-then-Verify)

Ek $n$ -bit SISO shift register ke liye, jo bit ab enter karti hai woh $n$ clock edges ke baad output pe dikhti hai — har stage ke liye ek edge.

Worked Examples

Clock	$Q_{3} Q_{2} Q_{1} Q_{0}$	Yeh step kyun?
start	1011	initial
1	0101	har bit ek jagah right move hoti hai; MSB←0
2	0010	phir se right slide; trailing 1 drop ho jaata hai
3	0001	har shift pe value half: 11→5→2→1

Kyun? Right shift by 1 = integer 2 se divide. $11 \to 5 \to 2 \to 1$ ✔ (truncated division se match karta hai).

Clock	Serial In	$Q_{3} Q_{2} Q_{1} Q_{0}$	Yeh step kyun?
0	–	0000	cleared
1	1	0001	pehla bit $Q_{0}$ mein aata hai
2	0	0010	purana bit upar shift hota hai, naya 0 enter karta hai
3	1	0101	chalte rehte hain
4	1	1011	poora word assemble hua → parallel mein padho

Kyun? 4 clocks ke baad 4 serial bits ek parallel word $1011$ ke roop mein baith jaate hain — yahi serial→parallel conversion hai.

Common Mistakes

Active Recall

Recall Ek 12-saal ke bachche ko explain karo (Feynman)

Socho ek line mein bachche khade hain jिnमें se har ek ek card pakde hua hai. Ek register woh hai jab, ek seeti par, har bachche ko ek saath ek naya card diya jaata hai — ab woh saath milke ek poori hand yaad rakhte hain. Ek shift register woh hai jab, har seeti par, har bachcha apna card daayein wale bachche ko pass karta hai, aur dum waale bachche ko ek naya card diya jaata hai. Kaafi seetiyon ke baad, jo card aapne ek end mein daala tha woh chalte chalte doosre end tak pahunch jaata hai aur gir jaata hai. Cards ko ek step pass karna = number double ya half hota hai, aur cards ko ek ek karke pass karna aapko ek poori hand ek tang chhote raaste se bhejna deta hai.

Flashcards

n

D flip-flops ka ek set jo ek common clock pe hote hain aur ek

n

-bit word parallel mein load karke store karte hain.

Ek register ko shift register kya banata hai?

Har flip-flop ka D input pichle flip-flop ke output se fed hota hai (

D_{i} = Q_{i - 1}

), isliye bits har clock pe ek position move karte hain.

Ek register mein saare flip-flops ko ek clock kyun share karni chahiye?

Taaki saare bits simultaneously (atomically) update hon, glitch/mixed-state words se bachne ke liye.

Load-enable waale register ki equation?

D_{f f} = L O A D \cdot D + \overline{L O A D} \cdot Q

; LOAD=1 hone par

D

load karta hai, LOAD=0 hone par hold karta hai.

Left shift kaunsi arithmetic operation karta hai?

2 se multiply karta hai (har bit ek higher power-of-2 position pe jaata hai), agar koi overflow na ho.

Unsigned right shift numerically kya karta hai?

Floor division by 2 (LSB discard ho jaata hai).

Ek bit ko ek n-bit SISO register traverse karne mein kitne clocks lagte hain?

n clock edges (har stage ke liye ek).

Shift register ke chaar I/O types kaunse hain?

SISO, SIPO, PISO, PIPO (Serial/Parallel In × Serial/Parallel Out).

Kaunsa type serial data ko parallel word mein convert karta hai?

SIPO (Serial-In Parallel-Out).

Kaunsa type stored word ko ek bit at a time transmit karta hai?

PISO (Parallel-In Serial-Out).

Ek signed number ke liye, kaunsa right shift value preserve karta hai?

Arithmetic right shift — sign bit ko MSB mein copy karo.

Connections

D flip-flop — har register ka building atom
Multiplexers — load-enable / mode-select kaise build hota hai
Counters — ek ring/Johnson counter shift register with feedback hota hai
Serial communication (UART, SPI) — SIPO/PISO packing/unpacking karte hain
Binary multiplication and division — shift-and-add shift registers use karta hai
Clocking and setup/hold time — kyun common clock timing meet karni chahiye