Clock skew and jitter — Hinglish notes

3.4.15 · Hardware › Sequential Circuits

WHAT — hum kya baat kar rahe hain?

Key distinction (yeh yaad karo):

	Skew	Jitter
Nature	Spatial (FF-to-FF)	Temporal (edge-to-edge)
Deterministic?	Haan (fixed offset)	Nahi (random)
Root cause	Unequal clock paths	Oscillator/supply noise

WHY — yeh matter kyun karta hai? (First-principles timing)

Ek flip-flop ko data stable chahiye clock edge ke aas-paas ek window mein:

Setup time $t_{s u}$ : data edge se pehle aana chahiye.
Hold time $t_{h}$ : data edge ke baad stable rehna chahiye.

Socho launch FF1 → combinational logic → capture FF2, clock period $T$ .

SETUP constraint derive karna (skew ke saath)

FF1 edge dekhta hai $t = 0$ par. FF2 agli edge nominally $t = T$ par dekhta hai, lekin $t_{s k e w}$ se skewed, toh FF2 ki capturing edge hai $T + t_{s k e w}$ par.

Data FF2 ke D input par valid hai time par: $t_{d a t a} = t_{c q} + t_{l o g i c}$

Requirement: data setup window se pehle settle ho jaaye: $t_{c q} + t_{l o g i c} + t_{s u} \leq T + t_{s k e w}$

Ab jitter add karo — yeh worst case mein capture edge ko $t_{j i tt er}$ se pehle push kar sakta hai (edge jaldi aati hai, kam time milta hai): $t_{c q} + t_{l o g i c} + t_{s u} + t_{j i tt er} \leq T + t_{s k e w}$

HOLD constraint derive karna (skew ke saath)

Hold usi same edge ke baare mein hai jo ek race create karti hai: FF1 se $t = 0$ par launch hone wala naya data FF2 par itni jaldi nahi aana chahiye ki yeh corrupt kare jo FF2 apni khud ki edge par capture karne ki koshish kar raha hai.

FF2 ki capturing edge hai $t_{s k e w}$ par (same edge, skewed). Naya data FF2 par aata hai $t_{c q} + t_{l o g i c, min}$ par. Yeh hold window band hone ke baad aana chahiye: $t_{c q} + t_{l o g i c, min} \geq t_{s k e w} + t_{h}$

Jitter add karo (edge late aa sakti hai, hold ko $t_{j i tt er}$ se aur bura banaa ke): $t_{c q} + t_{l o g i c, min} \geq t_{s k e w} + t_{h} + t_{j i tt er}$

HOW — skew ka sign kaise samjhein

Worked Examples

Common Mistakes

Flashcards

Clock skew define karo.

Same clock se aane wale do flip-flops ke beech clock-edge arrival time mein spatial, deterministic difference, unequal clock-tree paths ki wajah se.

Clock jitter define karo.

Ek clock edge ka ideal position se temporal, random cycle-to-cycle variation, oscillator/PLL/supply noise ki wajah se.

Skew aur jitter ke saath setup constraint?

t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} \leq T + t_{s k e w}

Skew aur jitter ke saath hold constraint?

t_{c q} + t_{l o g i c, min} \geq t_{s k e w} + t_{h} + t_{j i tt er}

Clock frequency kam karke hold violation kyun fix nahi hota?

Hold inequality mein koi period

T

nahi hota; yeh same cycle mein edge-vs-edge race hai,

T

se independent.

Positive skew setup ko help ya hurt karta hai?

Help karta hai — late capture edge data ko zyada time deti hai.

Positive skew hold ko help ya hurt karta hai?

Hurt karta hai — late capture edge fast naye data ko hold window violate karne ka mauka deta hai.

Kya jitter kabhi timing help karta hai?

Nahi — random hone ki wajah se, worst-case jitter hamesha setup aur hold dono ka margin kam karta hai.

Uncertainty ke saath

f_{ma x}

formula?

f_{ma x} = 1/ (t_{c q} + t_{l o g i c, ma x} + t_{s u} + t_{j i tt er} - t_{s k e w})

Hold violation kaise fix karein?

Data path mein delay/buffers add karo (

t_{l o g i c, min}

badhao) ya clock skew kam karo.

Recall Feynman: 12-saal ke bachche ko samjhao

Socho ek relay race jahan ek seeti sabko daudne ka signal deti hai. Ideally sabko seeti bilkul usi instant mein sunti hai. Skew tab hota hai jab seeti ki echo kuch runners tak thodi der se pahunche kyunki woh door khade hain — hamesha same delay. Jitter tab hota hai jab timekeeper ka haath kaanpe, toh seeti thodi jaldi ya thodi der se baje har baar — random. Agar runners thoda galat time par shuru karein, toh kuch log baton bahut jaldi de dete hain (hold problem) ya agla runner abhi ready nahi hota (setup problem). Engineers extra time chodh dete hain taaki koi bhi handoff kharaab na kare.

Connections

Setup and Hold Time — timing windows jo skew/jitter erode karte hain.
Flip-Flops — storage elements jo clock ho rahe hain.
Clock Distribution Network / Clock Tree — skew ka physical source.
Phase Locked Loop (PLL) — jitter ka main source.
Maximum Clock Frequency — jitter aur negative skew se directly kam hoti hai.
Static Timing Analysis — jahan yeh constraints check hoti hain.
Metastability — kya hota hai jab setup/hold violate ho jaaye.