What is a Verilog module vs a VHDL entity/architecture?
module bundles interface + behaviour together; VHDL separates the interface (entity, ports) from the internal behaviour (architecture).
Which assignment type for combinational logic in always @(*)?
Blocking =.
Which assignment type inside always @(posedge clk)?
Non-blocking <=.
Why does non-blocking <= model flip-flops correctly?
All right-hand sides are sampled first, then all left-hand sides update together — matching parallel edge-triggered registers.
What creates a continuous combinational connection in Verilog?
assign y = f(inputs); (continuous assignment).
Why must a signal driven in an always block be reg?
It must hold its value between events; reg is a variable-type storage in Verilog.
What does 8'hA5 mean?
An 8-bit-wide literal in hexadecimal, value 10100101.
What is an inferred latch and how do you avoid it?
A memory element created when a combinational output isn't assigned on every path; avoid by defaulting/assigning all outputs in all branches.
Are two separate assign statements ordered?
No — they are concurrent hardware, order on the page is irrelevant.
What does {4'b1010, 4'b0101} produce?
Concatenation → the 8-bit value 10100101.
Recall Feynman: explain to a 12-year-old
Imagine you're describing a machine to a robot builder using only text. You could say "this wire is always the AND of these two buttons" — that wire never sleeps, it reacts instantly (that's assign). Or you could say "every time the bell rings, remember what's on this wire" — that's a memory box that only updates on the bell (the clock edge). The tricky part: when the bell rings, all memory boxes look at their inputs at the same instant and then flip together — so we write <= to mean "everybody, grab your value now, and swap simultaneously," instead of = which means "do this one right now before the next line."
Dekho, HDL (Verilog ya VHDL) ka sabse bada point yeh hai: yeh code nahi, hardware ki description hai. Matlab jab tum assign y = a & b; likhte ho, tumne ek AND gate ka wire bana diya — woh line kabhi "run" nahi hoti, woh hamesha zinda hai, a ya b badla toh y turant update. Isliye do alag assign statements ka order matter nahi karta — dono ek saath, parallel mein exist karte hain, jaise board pe do alag gate soldered ho.
Ab dusra important cheez: blocking = vs non-blocking <=. Simple rule yaad rakho — jab bhi always @(posedge clk) (clock edge) ho, to <= use karo; jab combinational logic always @(*) ho, to = use karo. <= ka matlab hai "sab flip-flop ek saath apna input pakdo, phir ek saath update karo" — real hardware bilkul aise hi kaam karta hai. Isi wajah se a <= b; b <= a; sach mein swap karta hai, jabki = se dono b ban jaate.
VHDL thoda alag hai: interface ko entity mein likhte ho (ports, direction in/out), aur andar ka kaam architecture mein. Verilog dono ko ek module mein daal deta hai. Baaki concept same — concurrent hardware, clocked registers.
Ek beginner trap yaad rakhna: agar combinational block mein har output ko har branch mein assign nahi kiya, toh tool ek latch bana deta hai jo tum chahte hi nahi the. Solution — always @(*) use karo aur har output ko default value do. Bas yeh basics pakad lo, phir FSM, counters, sab isi pe build hote hain.
