Testbenches and simulation

WHY does this exist?

WHAT are the pieces?

HOW do you build one — derived from scratch

Let's build a TB step by step for a DUT, reasoning about why each line must exist.

Suppose our DUT is a 4-bit synchronous counter:

module counter(input clk, input rst, output reg [3:0] q);
  always @(posedge clk)
    if (rst) q <= 0; else q <= q + 1;
endmodule

Step 1 — a module with no ports.

module tb;

Why? A TB is the top of the hierarchy; there is nothing above it to wire ports to.

Step 2 — declare TB-side signals.

  reg clk, rst;      // we DRIVE these → reg
  wire [3:0] q;      // DUT drives this → wire

Why? clk and rst are outputs of the TB into the DUT, so the TB must hold/assign them → reg. q is driven by the DUT → wire.

Step 3 — instantiate the DUT (connect the rig to the thing under test).

  counter dut(.clk(clk), .rst(rst), .q(q));

Why? Named port connection (.port(signal)) is safer than positional — order changes won't silently mis-wire.

Step 4 — generate a clock.

  initial clk = 0;
  always #5 clk = ~clk;   // period = 10 time units, 100 MHz if 1 unit = 1 ns

Why? Sequential logic needs a posedge. Toggling every 5 units gives a 10-unit period. The always runs forever, which is what a clock must do.

Step 5 — stimulus + self-checking.

  integer expected;
  initial begin
    rst = 1; expected = 0;
    @(posedge clk); #1;          // apply reset for one cycle
    rst = 0;
    repeat (20) begin
      @(posedge clk); #1;        // wait for the flip-flop to update, then check
      expected = expected + 1;
      if (q !== expected[3:0])
        $error("t=\%0t: q=\%0d expected=\%0d",$time, q, expected[3:0]);
    end
    $display("TEST DONE");
    $finish;                     // stop the (otherwise infinite) simulation
  end

Why the #1 after @(posedge clk)? At the exact clock edge the flip-flop's new value hasn't settled in the same delta step — sampling a hair after the edge avoids a race condition and reads the stable value. Why !== not !=? !== also catches x/z (unknown/high-Z), which != treats as ambiguous.

Step 6 — waveform dump (Dual Coding for your eyes).

  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   // record everything under tb
  end

Why? When the self-check fails, the VCD waveform lets you see the timing relationship that broke.

The event-driven simulation model (the real engine)

Blocking (=) vs non-blocking (<=) — a testbench trap

Types of testbenches (know these names)

Worked example 2 — combinational DUT (a 2-input AND gate), exhaustive TB

DUT: module and2(input a,b, output y); assign y = a & b; endmodule

module tb;
  reg a, b; wire y;
  and2 dut(.a(a), .b(b), .y(y));
  integer i;
  initial begin
    for (i = 0; i < 4; i = i + 1) begin
      {a, b} = i[1:0];   // Why? concatenation drives both inputs from a counter
      #10;               // Why? let the combinational output settle before checking
      if (y !== (a & b))
        $error("a=%b b=%b y=%b", a, b, y);
    end
    $display("AND2 OK"); $finish;
  end
endmodule

Why exhaustive? A 2-input gate has only $2^2 = 4$ input combinations — cheap to test all of them. In general an $n$-input combinational block has $2^n$ cases; exhaustive testing is only feasible for small $n$, which is why random/coverage methods exist for large designs.

Worked example 3 — using a golden reference model

To test an adder, compute the expected sum in the TB itself:

reg [7:0] a, b; wire [8:0] sum;
adder8 dut(.a(a), .b(b), .sum(sum));
initial begin
  repeat (1000) begin
    a = $random; b = $random;   // Why? constrained-random-ish coverage
    #1;
    if (sum !== (a + b))        // Why? {a+b} in TB is the golden model
      $error("%0d + %0d = %0d", a, b, sum);
  end
  $finish;
end

Why this works: the simulator's own integer arithmetic is our trusted reference; the DUT's gate-level logic is what we distrust. Comparing the two automatically finds mismatches over 1000 random cases.

Active recall

Connections

• HDL Basics — Verilog and VHDL
• Blocking vs Non-blocking Assignments
• Synthesizable vs Non-synthesizable Constructs
• Digital Design Flow — Spec to Silicon
• Clocking and Sequential Logic
• SystemVerilog Assertions (SVA)
• Functional Coverage and Verification

Concept Map

Hinglish (regional understanding)