Before you can read a single line of the parent note, you must own the words and symbols it throws around. Below, every symbol is built from nothing: plain words → the picture it makes → why the topic can't live without it. Read top to bottom; each rung of the ladder rests on the one before.
Look at the picture. A signal is not a number — it is a number-that-varies-over-time. That single fact is why hardware is hard to test: a software variable has one value "now"; a hardware signal has a whole history. The testbench's entire job is to control that history for the inputs and inspect that history for the outputs.
Now that a signal is a value-over-time, ask: who writes to it? HDL splits signals into two kinds by who has the pen.
This is exactly the rule the parent note states in "Regs vs wires in a TB". See Blocking vs Non-blocking Assignments for how reg values actually get updated in time.
Every arrow means "you must understand the tail before the head makes sense." The parent topic Testbenches and Simulation sits at the bottom because it depends on all of these.
Cover the right side; can you answer each before moving on?
What is a signal, in one sentence?
A named wire carrying a value that changes over time — the horizontal axis is time, the height is 0 or 1.
Name the four logic values and what x and z mean.
0, 1, x (unknown), z (high-impedance / floating).
In a testbench, which signals are reg and which are wire?
Inputs you drive → reg; DUT outputs you observe → wire.
What does #10 do, and is it real seconds?
Advance simulation time by 10 abstract units; it is not wall-clock time.
Why is the clock period 2d if you toggle every d?
One toggle is only half a wave; you need two toggles (up + down) to complete a cycle.
Difference between != and !==?
!= returns x if either side is x/z; !== compares exactly and flags x/z as a real mismatch.
When does initial run vs always?
initial runs once at start; always repeats forever (used for the clock).
Why is a testbench non-synthesizable?
It's built from $-tasks and delays that only exist inside the simulator, with no silicon equivalent.
What is a delta cycle?
A zero-time sub-step ordering signal updates at the same simulation time, without advancing time.
Recall Self-test: build the skeleton from memory
Can you, from a blank page, write module tb;, declare reg clk, rst; wire [3:0] q;, instantiate the DUT with named ports, make a clock with always #5 clk = ~clk;, and end with $finish;? If yes, you're ready for the parent note.
