Testbenches and simulation

3.5.5 · Hardware › HDL & Digital Design Flow

WHY yeh cheez exist karti hai?

WHAT — pieces kya hain?

HOW — scratch se kaise banate hain

Chaliye ek TB ko step by step banate hain ek DUT ke liye, yeh sochte hue ki har line kyun zaruri hai.

Maan lo humara DUT ek 4-bit synchronous counter hai:

module counter(input clk, input rst, output reg [3:0] q);
  always @(posedge clk)
    if (rst) q <= 0; else q <= q + 1;
endmodule

Step 1 — bina ports ka ek module.

module tb;

Kyun? Ek TB hierarchy ka top hota hai; uske upar kuch nahi hota jo ports se wire kiya ja sake.

Step 2 — TB-side signals declare karo.

  reg clk, rst;      // hum inhe DRIVE karte hain → reg
  wire [3:0] q;      // DUT ise drive karta hai → wire

Kyun? clk aur rst TB ke DUT mein jaane wale outputs hain, isliye TB ko unhe hold/assign karna padta hai → reg. q DUT drive karta hai → wire.

Step 3 — DUT instantiate karo (rig ko test wali cheez se connect karo).

  counter dut(.clk(clk), .rst(rst), .q(q));

Kyun? Named port connection (.port(signal)) positional se zyada safe hai — order change hone par silently mis-wire nahi hoga.

Step 4 — clock generate karo.

  initial clk = 0;
  always #5 clk = ~clk;   // period = 10 time units, 100 MHz agar 1 unit = 1 ns

Kyun? Sequential logic ko posedge chahiye. Har 5 units mein toggle karne se 10-unit period milta hai. always hamesha chalta rehta hai, jo ek clock ke liye zarurihai.

Step 5 — stimulus + self-checking.

  integer expected;
  initial begin
    rst = 1; expected = 0;
    @(posedge clk); #1;          // reset ko ek cycle ke liye apply karo
    rst = 0;
    repeat (20) begin
      @(posedge clk); #1;        // flip-flop update hone ka wait karo, phir check karo
      expected = expected + 1;
      if (q !== expected[3:0])
        $error("t=\%0t: q=\%0d expected=\%0d",$time, q, expected[3:0]);
    end
    $display("TEST DONE");
    $finish;                     // (warna infinite) simulation band karo
  end

@(posedge clk) ke baad #1 kyun? Exact clock edge pe flip-flop ki nayi value same delta step mein settle nahi hui hoti — edge ke thodi der baad sampling karna ek race condition se bachata hai aur stable value padhta hai. !== kyun na ki !=? !== x/z (unknown/high-Z) ko bhi pakadta hai, jo != ambiguous maanta hai.

Step 6 — waveform dump (aankho ke liye Dual Coding).

  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   // tb ke neeche sab kuch record karo
  end

Kyun? Jab self-check fail ho, VCD waveform aapko woh timing relationship dikhata hai jo tooti.

Event-driven simulation model (asli engine)

Blocking (=) vs non-blocking (<=) — ek testbench trap

Testbenches ke types (yeh names yaad rakho)

Worked example 2 — combinational DUT (ek 2-input AND gate), exhaustive TB

DUT: module and2(input a,b, output y); assign y = a & b; endmodule

module tb;
  reg a, b; wire y;
  and2 dut(.a(a), .b(b), .y(y));
  integer i;
  initial begin
    for (i = 0; i < 4; i = i + 1) begin
      {a, b} = i[1:0];   // Kyun? concatenation dono inputs ko ek counter se drive karta hai
      #10;               // Kyun? check karne se pehle combinational output settle hone do
      if (y !== (a & b))
        $error("a=%b b=%b y=%b", a, b, y);
    end
    $display("AND2 OK"); $finish;
  end
endmodule

Exhaustive kyun? Ek 2-input gate mein sirf $2^2=4$ input combinations hain — sab ko test karna sasta hai. Generally ek $n$-input combinational block mein $2^n$ cases hote hain; exhaustive testing sirf chhote $n$ ke liye feasible hai, isliye bade designs ke liye random/coverage methods exist karte hain.

Worked example 3 — golden reference model use karna

Ek adder test karne ke liye, expected sum TB mein khud compute karo:

reg [7:0] a, b; wire [8:0] sum;
adder8 dut(.a(a), .b(b), .sum(sum));
initial begin
  repeat (1000) begin
    a = $random; b = $random;   // Kyun? constrained-random-ish coverage
    #1;
    if (sum !== (a + b))        // Kyun? TB mein {a+b} golden model hai
      $error("%0d + %0d = %0d", a, b, sum);
  end
  $finish;
end

Yeh kyun kaam karta hai: simulator ka khud ka integer arithmetic humara trusted reference hai; DUT ka gate-level logic woh hai jis par hum trust nahi karte. Dono ko automatically compare karna 1000 random cases mein mismatches dhundh leta hai.

Active recall

Connections

• HDL Basics — Verilog and VHDL
• Blocking vs Non-blocking Assignments
• Synthesizable vs Non-synthesizable Constructs
• Digital Design Flow — Spec to Silicon
• Clocking and Sequential Logic
• SystemVerilog Assertions (SVA)
• Functional Coverage and Verification

Concept Map