RTL (register transfer level) design

HOW does data actually flow? (Derive the timing)

Formula The clock-period constraint (derived, not dumped)

The captured value must be stable a setup time before the edge. Between two edges we have one clock period $T$ . The signal path budget is: $T \;\ge\; t_{cq} + t_{comb} + t_{setup}$ WHY each term?

$t_{cq}$ (clock-to-Q): after the edge, R1's output isn't valid instantly; it takes $t_{cq}$ to appear.
$t_{comb}$ : the combinational logic between R1 and R2 needs time to compute.
$t_{setup}$ : R2 needs its input stable this long before the edge to reliably latch. Rearranged, the max clock frequency is: $f_{max} = \frac{1}{t_{cq} + t_{comb,max} + t_{setup}}$ The slowest path (largest $t_{comb}$ ) is the critical path — it sets your speed.

Worked Example 1 — A simple accumulator

Design: acc <= acc + data_in; on each clock.

module accum(input clk, input rst, input [7:0] data_in,
             output reg [7:0] acc);
  always @(posedge clk) begin
    if (rst) acc <= 8'd0;      // synchronous reset
    else     acc <= acc + data_in;
  end
endmodule

Step: use <= (non-blocking). Why this step? Non-blocking assignment schedules the update at the end of the timestep, modeling "all registers latch simultaneously on the edge." Real flip-flops all fire together — <= matches that. Using = here would create a false ordering dependency.

Step: reset inside @(posedge clk). Why? This is a synchronous reset — it only takes effect on an edge, exactly like real logic feeding the D input.

Timing: critical path = adder. If $t_{cq}=0.2$ ns, adder $t_{comb}=1.5$ ns, $t_{setup}=0.3$ ns, then $T\ge 2.0$ ns, so $f_{max}=500$ MHz.

Worked Example 2 — Combinational vs sequential split

Compute y = (a + b) * c, registered output.

reg [15:0] y;
wire [15:0] prod = (a + b) * c;   // combinational (assign-style)
always @(posedge clk) y <= prod;  // sequential: latch it

Step: keep the arithmetic combinational, latch only at the end. Why? Separating "compute" (a pure function, no clock) from "store" (the register) is the essence of RTL. The tool synthesizes an adder + multiplier as gates, then one register bank.

Forecast-then-Verify: Predict — how many registers? Only the 16-bit y → 16 flip-flops. The adder/multiplier are gates, not registers. ✅ (Beginners often think every wire is stored — it isn't.)

Worked Example 3 — Blocking mistake in sequential logic

// BUGGY intent: swap a and b every clock
always @(posedge clk) begin
  a = b;   // blocking
  b = a;   // now b gets the NEW a, not old a!
end

a=b executes, then b=a sees the already-updated a. Both become old b. Fix:

always @(posedge clk) begin
  a <= b;
  b <= a;   // both use OLD values → true swap
end

Why the fix works: non-blocking reads all right-hand sides using pre-edge values, then updates simultaneously — a faithful register model.

Common mistake Steel-manned common mistakes

1. "Use = in sequential blocks, it's simpler." Why it feels right: in software, = is normal assignment and order is obvious. The truth: real flip-flops update in parallel on the edge; blocking = imposes a sequential order that doesn't exist in hardware → simulation-synthesis mismatch and swap bugs. Fix: <= for sequential (posedge), = for combinational (always @(*)).

2. "I can make it faster just by raising the clock." Why it feels right: clocking faster = more work/sec. The truth: if $T < t_{cq}+t_{comb}+t_{setup}$ , logic hasn't settled → setup violation → garbage. Fix: shorten the critical path (pipeline it) first, then raise $f$ .

3. "Every signal I name becomes a register." Why it feels right: variables in code "hold" values. The truth: only signals assigned in @(posedge clk) (or with feedback) become registers; combinational assigns are just wires/gates. Fix: ask "does this need to remember across a clock?" If no → combinational.

4. "A slow clock fixes hold violations." Why it feels right: slower clock fixes setup, seems symmetric. The truth: hold constraint $t_{cq}+t_{comb,min}\ge t_{hold}$ has no $T$ in it. Fix: add delay buffers on the short path.

Recall Feynman: explain to a 12-year-old

Imagine a relay race. Registers are runners standing at fixed spots holding a baton (a number). The clock is a whistle. On every whistle, each runner hands the baton to the next runner. But between whistles, the baton passes through a little machine (the logic) that changes it — maybe adds 1. The whole trick: the machine must finish changing the baton before the next whistle blows, or the next runner grabs a half-cooked number. Blow the whistle too fast → chaos. RTL is just writing down: "at each whistle, this runner gets this changed baton."

Flashcards

What does RTL stand for and describe?

Register Transfer Level — describes hardware as registers (state) plus combinational logic transferring data between them on each clock edge.

The two fundamental building blocks in RTL?

Combinational logic (no memory, pure function of inputs) and sequential logic (registers updated on the clock edge).

Write the max-clock-period (setup) constraint.

T \ge t_{cq} + t_{comb,max} + t_{setup}

Why does the critical path determine max frequency?

It's the slowest combinational path between registers; the clock period must exceed its delay (plus

t_{cq}+t_{setup}

), so it caps

f_{max}

Why use non-blocking (<=) in @(posedge clk) blocks?

It models all flip-flops latching simultaneously using pre-edge values, matching real parallel register updates; blocking = imposes false ordering.

Write the hold-time constraint and note what's special.

t_{cq} + t_{comb,min} \ge t_{hold}

— it has no

T

, so slowing the clock cannot fix hold violations.

Which signals become registers in synthesis?

Only those assigned under a clock edge (or needing to remember state across clocks); combinational assigns become gates/wires.

How do you make a design run at a higher clock frequency?

Shorten the critical path (e.g., pipeline it), reducing

t_{comb,max}

; then raise

f

Difference between synchronous and asynchronous reset (RTL)?

Sync reset is inside @(posedge clk) and acts only on an edge; async reset is in the sensitivity list and acts immediately.

Connections

HDL & Digital Design Flow
Verilog syntax and semantics
Combinational logic design
Sequential logic and flip-flops
Logic synthesis
Static Timing Analysis
Pipelining
Finite State Machines
Clock domains and metastability

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, RTL ka matlab hai apne circuit ko is tarah describe karna: "har clock edge pe, kaunsa register kaunsi value store karega." Do hi cheezein hoti hain — registers (jo numbers yaad rakhte hain) aur combinational logic (jo bina yaad rakhe seedha compute karti hai, jaise adder). Data ek register se nikalta hai, beech ki logic se hoke guzarta hai (add, multiply, jo bhi), aur agli clock edge pe doosre register mein "latch" ho jaata hai. Bas yahi hai poora khel.

Sabse important baat timing hai. Register se signal nikalne mein $t_{cq}$ lagta hai, logic ko compute karne mein $t_{comb}$ , aur next register ko capture ke liye pehle $t_{setup}$ chahiye. In sabka total clock period $T$ se kam hona chahiye: $T \ge t_{cq}+t_{comb}+t_{setup}$ . Jo path sabse slow hai wo critical path hai — wahi tumhari maximum speed decide karta hai. Agar clock bahut fast kar doge, logic settle nahi hogi aur galat value latch ho jaayegi.

Verilog mein ek golden rule yaad rakho: sequential block (always @(posedge clk)) mein hamesha <= (non-blocking) use karo, aur combinational (always @(*)) mein = (blocking). Kyun? Kyunki real flip-flops sab ek saath, ek hi edge pe update hote hain — <= yahi parallel behaviour model karta hai. Agar = use karoge sequential mein, to swap type bugs aa jaayenge. RTL master karne ke liye bas yeh soch: "kya is signal ko clock ke aar-paar yaad rakhna hai?" Haan → register. Nahi → sirf logic.

WHY does RTL exist?

WHAT is RTL, precisely?

HOW does data actually flow? (Derive the timing)

Worked Example 1 — A simple accumulator

Worked Example 2 — Combinational vs sequential split

Worked Example 3 — Blocking mistake in sequential logic

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — HDL & Digital Design Flow

Connections