Intuition The one core ideaA digital circuit is nothing more than boxes that remember numbers (registers) wired together by logic that changes numbers (gates), with a shared drumbeat (the clock) telling every box "update now!" all at once. RTL design is the art of writing down which box gets which changed number on each drumbeat — and everything below is just the vocabulary you need to say that sentence precisely.
This page assumes you have seen nothing . We build every word the parent RTL note leaned on, one brick at a time, each brick resting on the last.
A bit is a single wire that is either high (call it 1 low (call it 0 only thing a digital wire ever carries at one instant.
Think of a light switch on a wall: it is up or down, nothing in between. A bit is that switch frozen at one moment. A bus is just many switches side by side — an 8-bit bus is 8 switches, so it can show any pattern from 00000000 to 11111111.
Why does the topic need this? Every register and every logic output is ultimately a bundle of these on/off wires. When the parent writes [7:0] acc it means "a bundle of 8 bits, numbered 7 down to 0."
[7:0]
In Verilog [7:0] means "a group of 8 wires, indexed from bit 7 (the most significant , worth the most) down to bit 0 (the least significant , worth 1)." The number they represent is bit 7 ⋅ 2 7 + bit 6 ⋅ 2 6 + ⋯ + bit 0 ⋅ 2 0
Look at the figure: each switch has a weight printed below it (128 , 64 , 32 , … , 1 0 2 8 − 1 = 255
Definition Combinational logicCombinational logic is any arrangement of gates whose output depends only on the inputs present right now . Change an input, and after a tiny settling delay the output follows. It cannot remember anything.
Imagine a coffee machine: press "espresso" and coffee comes out; press "tea" and tea comes out. The machine has no memory — it does not care what you pressed a minute ago, only what is pressed now . That is a pure function: same input → same output, every time.
Why does the topic need this? The parent's δ λ built entirely from combinational logic . When you write sum = a + b, an adder made of these gates is what actually appears in silicon. See Combinational logic design for the full gate zoo.
Definition Propagation delayt co mb t co mb 1 ns = 1 0 − 9 travel time before the last one falls.
This delay is the whole reason the clock cannot go infinitely fast, which we reach in §4.
Definition Register (D flip-flop)A register is a one-bit (or multi-bit) memory box with two doors: a D input (the value waiting to enter) and a Q output (the value currently stored). Its single rule: on the clock edge, copy whatever is on D into Q; between edges, hold Q perfectly still.
Think of a camera that takes one photo every time a whistle blows. Whatever the scene is at the whistle gets frozen and displayed until the next whistle. The scene (D) can change wildly between whistles — the photo on the wall (Q) does not change until the next click.
In the figure the blue staircase is Q. Notice it only steps at the tall clock ticks, and it steps to whatever D was at that instant — ignoring everything D did in between. That "sample and hold" behaviour is the entire definition of memory in RTL. Deep dive: Sequential logic and flip-flops .
Definition Clock and clock edgeThe clock is a special wire that marches 0 , 1 , 0 , 1 , 0 , 1 , … clock edge is the moment it flips. A rising (or posedge ) edge is the 0 → 1
T f period T 2 ns frequency f f = T 1 T = 2 ns f = 2 × 1 0 − 9 s 1 = 500 000 000 Hz = 500 MHz .
Intuition Why a shared clock at all?If every box updated whenever it felt like it, a number could be half-changed while the next box is reading it — chaos. The clock is a conductor's baton : everyone plays their note together , so each box always reads a fully-settled value. This is the "synchronous" in synchronous design.
Why the topic needs it: the parent's whole timing law (T ≥ t c q + t co mb + t se t u p fitting the work between two drumbeats . See Clock domains and metastability for what happens when signals cross between different drumbeats.
The parent hits you with t c q t se t u p t h o l d
t c q not appear instantly — the box needs a short moment t c q
t se t u p stable and unchanging for a little while before the edge , namely t se t u p before the shutter clicks — move too late and the photo blurs.
t h o l d also stay stable a little while after the edge, namely t h o l d after the click too.
Read the figure left to right: the shaded "keep-out" zone straddles the edge — t se t u p t h o l d outside that zone. This one picture is why both of the parent's timing inequalities exist.
Q t X t Q t t all values stored in all registers right now . X t external inputs right now. The subscript t which drumbeat we mean; t + 1
δ λ δ next-state function — combinational logic that looks at current state and inputs and computes what the registers should become :
Q t + 1 = δ ( Q t , X t ) . λ output function — combinational logic computing what the circuit shows to the outside:
Y t = λ ( Q t , X t ) .
δ λ is a digital machine.
This tuple is the formal skeleton of a finite state machine , and the whole synthesis flow (Logic synthesis ) is about turning δ λ
Next state delta and output lambda
Read top to bottom: bits build both logic and registers; the clock drives registers and sets timing; logic plus registers form the δ / λ is RTL, which you finally write as Verilog . Later chapters — Static Timing Analysis and Pipelining — grow directly out of the §4 timing box.
Self-test: cover the right side and answer before revealing.
What is a bit, physically? A single wire held at one of two voltages, read as 0 (low) or 1 (high).
What does [7:0] mean in Verilog? A bundle of 8 wires, bit 7 the most significant (weight 128) down to bit 0 (weight 1).
Define combinational logic in one sentence. Gates whose output depends only on the present inputs, with no memory of the past.
What is propagation delay t co mb The small time a gate/logic path takes to settle to its correct output after an input changes.
State the single rule of a D flip-flop. On the clock edge, copy D into Q; between edges, hold Q frozen.
What is a rising (posedge) clock edge? The moment the clock wire flips from 0 to 1, when all registers sample their D inputs.
How are period T f They are reciprocals: f = 1/ T T = 2 ns f = 500 MHz
What does t c q The delay after the edge before Q shows the newly captured value.
What must be true during the setup window t se t u p D must be stable and unchanging for that long before the edge, or capture is unreliable.
What must be true during the hold window t h o l d D must stay stable for that long after the edge, or the box latches garbage.
Write the setup timing inequality with every term named. t c q + t co mb + t se t u p ≤ T
What are Q t X t Q t t X t t
What do δ λ δ Q t + 1 = δ ( Q t , X t ) λ Y t = λ ( Q t , X t )
