RTL (register transfer level) design: Visual walkthrough

We will build up a two-register pipe: one register that sends a number, a block of logic that changes it, and one register that catches it. Everything below is a picture of that one story.

Step 1 — What a register even is

WHAT we set up: a box with D in, Q out, clock underneath. WHY it matters: everything in RTL is these boxes plus wires between them (see Sequential logic and flip-flops). If you understand one box's timing, you understand the whole chip. PICTURE: below, the flat blue line is Q staying frozen; it only jumps at the orange whistle marks — never in between.

$D$ ::: the number waiting at the input pin
$Q$ ::: the number the box currently remembers and shows at its output
clock edge ::: the single instant when $Q$ is allowed to become $D$

Step 2 — Two registers with logic in between

WHAT: R1 → logic lump → R2, all sharing one clock. WHY: this is the smallest circuit that can transfer data (the "T" in RTL). The parent's $Q_{t + 1} = δ (Q_{t}, X_{t})$ is literally this drawing: $δ$ is the logic lump, $Q$ lives in the registers. PICTURE: follow the number leaving R1 (blue), getting reshaped in the orange logic cloud, arriving at R2's door.

R1 ::: the register that sends — its Q is the starting number
logic cloud ::: combinational logic $δ$ , pure math with no clock of its own
R2 ::: the register that catches — its D pin receives the reshaped number

Step 3 — The output is not instant: meet $t_{c q}$

WHAT: we mark the gap between the edge and Q actually being ready. WHY this tool: we need a number for "how late is the data?" — because later we compare it against the whistle spacing. $t_{c q}$ is the first slice of the time budget. PICTURE: the orange dashed edge is the whistle at time 0; the blue Q signal only reaches its new level a little $t_{c q}$ later (green bracket).

Term-by-term:

The subscript $c q$ ::: "clock-to-Q" — from the clock edge to Q being valid
$t_{c q}$ ::: how long after the whistle before R1's new output is trustworthy

Step 4 — The logic takes time too: meet $t_{co mb}$

WHAT: add a second time slice, stacked after $t_{c q}$ . WHY: the number cannot arrive at R2 before it has both left R1 and finished the math. Delays in series add: $(time data reaches R2’s door) = t_{c q} + t_{co mb}$

$t_{c q}$ here ::: waiting for R1 to speak
$t_{co mb}$ here ::: waiting for the adder/multiplier cloud to settle
the "+" ::: two delays one after another simply sum

PICTURE: a timeline bar — first the blue $t_{c q}$ block, then the orange $t_{co mb}$ block laid end to end. The right edge of orange = the earliest the answer is fully ready at R2.

Step 5 — R2 is fussy: meet $t_{se t u p}$ and the deadline

WHAT: the next whistle sits at time $T$ (one clock period later). R2 demands the data be quiet by $T - t_{se t u p}$ . WHY this tool: $t_{se t u p}$ turns "arrive before the edge" into a precise deadline. It's the last slice of the budget. PICTURE: the timeline now runs whistle-to-whistle (length $T$ ). A red "no-go" zone of width $t_{se t u p}$ sits just before the second whistle — the data ramp (blue+orange) must finish left of that red zone.

$T$ ::: one clock period — the spacing between two whistles
$t_{se t u p}$ ::: the quiet time R2 needs before the edge to latch reliably
$T - t_{se t u p}$ ::: the actual deadline the arriving data must beat

Step 6 — Snap the pieces together: the setup constraint

Move $t_{se t u p}$ to the left and you have the parent's law:

WHAT: three slices stacked; they must not overflow the box of width $T$ . WHY: if they overflow, the number is still moving when R2 latches → it grabs garbage (a setup violation). PICTURE: the three coloured slices packed inside a box labelled $T$ , with slack (green) if it fits, or an overflow (red) if it doesn't.

The slowest cloud (largest $t_{co mb}$ ) is the critical path — it decides the smallest legal $T$ , hence the top speed: $f_{ma x} = \frac{1}{t _{c q} + t _{co mb, ma x} + t _{se t u p}}$

Step 7 — The opposite danger: arriving too early (hold)

WHAT: consider the shortest (fastest) path, $t_{co mb, min}$ , on the same edge. WHY a separate rule: this has nothing to do with $T$ — it's about one single edge. New data must arrive later than the hold window: $t_{c q} + t_{co mb, min} \geq t_{h o l d}$

$t_{co mb, min}$ ::: delay through the fastest path in the cloud
$t_{h o l d}$ ::: how long R2 needs its input frozen after the edge
no $T$ anywhere ::: slowing the clock does not help hold

PICTURE: on one whistle, a red hold-window just after the edge; the fast new data (orange) must land to the right of it. If it lands inside the red window → hold violation.

Step 8 — Degenerate & edge cases (never leave a gap)

Zero logic ( $t_{co mb} = 0$ , register straight to register). Setup becomes $T \geq t_{c q} + t_{se t u p}$ — still positive, so there's still a top speed. Hold becomes $t_{c q} \geq t_{h o l d}$ ; if $t_{c q} < t_{h o l d}$ the flop fails on its own — vendors design $t_{c q} > t_{h o l d}$ so this never happens.
Only combinational, no second register. Then there is no "catch" edge and no $T$ term at all — pure Combinational logic design, timed by propagation delay alone.
Critical path longer than $T$ . Setup violation → the fix is Pipelining: chop the long cloud with an extra register so each piece fits.
Two different clocks feeding R1 and R2. The single- $T$ picture breaks — this is a clock-domain crossing, needing synchronizers, not this formula.

WHAT: four degenerate branches, each with its behaviour. WHY: the reader must never meet a scenario we hid. PICTURE: a 2×2 panel, one mini-timeline per case, showing whether the budget still closes.

The one-picture summary

Everything above compressed into a single annotated timeline: two whistles a period $T$ apart, the three stacked setup slices under the arrow, and the tiny red hold window under the first whistle. If the blue+orange stack fits left of the setup deadline and the fast data lands right of the hold window — the circuit is correct at that speed.

Recall Feynman: tell the whole story to a 12-year-old

Two kids stand a few metres apart. The one on the left holds a card with a number. A whistle blows every few seconds. On each whistle, the left kid reads his card out loud — but he's slow, so it takes him a beat ( $t_{c q}$ ) to actually say it. A messenger then runs the number over to the right kid, changing it on the way (adding, multiplying) — that run takes a while ( $t_{co mb}$ ). The right kid is careful: he needs the number sitting in front of him a little before the next whistle so he can copy it down cleanly ( $t_{se t u p}$ ). So the whole thing — the left kid speaking, the messenger running, and the number resting — has to finish inside one whistle-gap ( $T$ ). Blow whistles too fast and the messenger is still running when the right kid copies → he writes garbage. That's the setup law. But there's a sneaky opposite problem: if the messenger is lightning fast, he might shove the new number at the right kid while the kid is still writing the old one down — that's the hold problem, and running whistles slower doesn't fix it; you have to make the fast messenger dawdle a bit. Two rules, one race.

Flashcards

Why does data leaving a register not appear instantly at the clock edge?

Because of the clock-to-Q delay

t_{c q}

— transistors take time to swing the output valid after the edge.

What three delays must fit inside one clock period

T

t_{c q}

(clock-to-Q) +

t_{co mb}

(logic settle) +

t_{se t u p}

(R2's required lead time)

\leq T

Why can't you fix a hold violation by slowing the clock?

The hold inequality

t_{c q} + t_{co mb, min} \geq t_{h o l d}

contains no

T

; you fix it by adding delay to the too-fast path.

What is the critical path?

The path with the largest

t_{co mb}

; it sets the minimum legal

T

and therefore

f_{ma x}