Worked examples — RTL (register transfer level) design

The scenario matrix

Every RTL problem lands in one of these case classes. Think of it as a checklist: if we solve one example per row, no scenario can surprise you.

The eight examples below cover A through H, one each, and Example 5 covers D+E together (the shift register is the cleanest place to see both).

Symbols used everywhere below — earn them once:

The figure above is the timeline every example reads off: whistle at $t$, output appears $t_{cq}$ later, logic settles $t_{comb}$ later, and the value must be steady $t_{setup}$ before the next whistle. The leftover gap is the slack.

Example 1 — Setup PASS with positive slack · cell A

Forecast: guess before reading — is the slack positive, zero, or negative? Roughly how big?

1. Add the demand of the path. $t_{cq}+t_{comb,max}+t_{setup}=0.2+1.5+0.3=2.0$ ns. Why this step? This sum is the minimum period the path can survive. It's the total time from one whistle to when the data is safely steady before the next.
2. Compare to the supply $T$. We have $T=3.0$ ns available, the path needs $2.0$ ns. Why this step? Setup is literally "does the whistle give enough time?" — a supply vs demand comparison.
3. Compute slack. $3.0-2.0=1.0$ ns positive. Why this step? Slack is the leftover margin; positive means safe.

Verify: $2.0\le 3.0$ ✓, so it passes. Units: all nanoseconds, slack $=+1.0$ ns. Sanity: we could shave $1.0$ ns off $T$ (run faster) before this path breaks.

Example 2 — Setup FAIL, then fix by pipelining · cell B

Forecast: guess the slack sign at $T=1.6$ ns, then guess whether cutting the logic in half rescues it.

1. Test the original path. Demand $=0.2+1.5+0.3=2.0$ ns, supply $T=1.6$ ns. Why? Same supply-vs-demand law.
2. Slack $=1.6-2.0=-0.4$ ns → FAIL. Why this matters: a negative slack means the data is still settling when the whistle blows — garbage gets latched. You cannot fix this by clocking faster.
3. Pipeline: cut $t_{comb}$ in half. Insert one register in the middle so each stage does $1.5/2=0.75$ ns of logic. Why this step? Each half now sees demand $=t_{cq}+0.75+t_{setup}=0.2+0.75+0.3=1.25$ ns.
4. Re-test. Slack $=1.6-1.25=+0.35$ ns → PASS. Why it works: shorter logic between registers = less to settle per clock. Throughput stays high; only latency grows by one clock.

Verify: original slack $=-0.4$ ns (fail), pipelined stage demand $=1.25$ ns, pipelined slack $=+0.35$ ns (pass). Units ns throughout. Sanity: halving $t_{comb}$ removed $0.75$ ns of demand, which more than covered the $0.4$ ns deficit.

Example 3 — Hold check on a short path · cell C

Forecast: hold has no $T$ in it. Guess pass or fail, and guess whether $T$ can rescue it.

1. Compute the earliest arrival of new data. $t_{cq}+t_{comb,min}=0.2+0.15=0.35$ ns after the edge. Why? Hold asks: how soon can the new value show up at the receiver? The fastest route decides.
2. Compare to the hold requirement. Need $\ge t_{hold}=0.5$ ns. We have only $0.35$ ns. Why? If new data arrives before the register finished capturing the old value, it corrupts the capture.
3. $0.35<0.5$ → HOLD FAIL by $0.15$ ns. Why $T$ can't help: $T$ never appears in $t_{cq}+t_{comb,min}\ge t_{hold}$. Slowing the clock changes nothing.
4. Fix: add a delay buffer of $\ge 0.15$ ns on the short path so arrival becomes $\ge 0.5$ ns. Why this step? We slow down the too-fast path (add $t_{comb,min}$) — the only lever hold responds to.

Verify: arrival $=0.35$ ns, requirement $0.5$ ns, deficit $=0.15$ ns. Add $0.15$ ns buffer → arrival $=0.50$ ns $=t_{hold}$ (exactly meets). Units ns.

Example 4 — The word problem: a real counter's max speed · cell G

Forecast: guess whether $f_{max}$ is closer to 100 MHz or 1 GHz before computing.

1. Find the minimum period. $T_{min}=t_{cq}+t_{comb,max}+t_{setup}=0.25+2.4+0.35=3.0$ ns. Why? The counter can go no faster than its worst path allows to settle.
2. Invert to frequency. $f_{max}=1/T_{min}$. Why this tool — reciprocal? Frequency is cycles per second; period is seconds per cycle. They are exact inverses, so $f=1/T$ is the only conversion.
3. Compute. $f_{max}=\frac{1}{3.0\times 10^{-9}\text{s}}=3.33\times 10^8$ Hz $=333.3$ MHz. Why the powers of ten? $3.0$ ns $=3.0\times 10^{-9}$ s; its reciprocal is $\approx 3.33\times 10^8$ Hz, and $10^8$ Hz $=100$ MHz.

Verify: $T_{min}=3.0$ ns, $f_{max}\approx 333.3$ MHz. Units: $1/\text{s}=\text{Hz}$. Sanity: $1/3$ ns $\to$ a third of a GHz $=333$ MHz — matches. Closer to 100 MHz than 1 GHz, as the 3 ns adder dominates.

Example 5 — Zero logic + blocking bug: a shift register · cells D & E

// Intended: q1 <- old q0,  q0 <- d   (a true shift)
// BUGGY (blocking):
always @(posedge clk) begin
  q0 = d;    // q0 updated first
  q1 = q0;   // q1 now sees the NEW q0 = d, not the old q0!
end

Forecast: after the blocking version, does q1 get the old q0 (a real 2-deep shift) or the new q0 (collapsed to 1 stage)? Guess before step 3.

1. Note the logic depth is zero. Between registers there's a plain wire, so $t_{comb,max}=0$ (case D). Why this matters: the register-to-register path is a pure baton pass — timing is trivial ($T\ge t_{cq}+t_{setup}$), but the ordering semantics of = vs <= still bite.
2. Trace the blocking version in order. q0 = d runs first, so q0 is now d. Then q1 = q0 reads the already-updated q0, so q1 = d too. Why? Blocking = executes top-to-bottom, using values as they've been updated within this pass.
3. Result: both registers hold d. The 2-deep shift collapsed into 1 stage — the old q0 was lost.
4. Fix with non-blocking <=.

   always @(posedge clk) begin
     q0 <= d;
     q1 <= q0;   // reads OLD q0 (pre-edge), then all latch together
   end

   Why it works: <= reads all right-hand sides using pre-edge values, then updates simultaneously — exactly how real flip-flops fire in parallel. Now q1 correctly gets the old q0, giving a genuine 2-deep shift.

Verify: feed d = 1,0,0,.... Blocking: clock1 → q0=1,q1=1; clock2 → q0=0,q1=0 (the 1 never reappears at q1 one cycle late → NOT a shift). Non-blocking: clock1 → q0=1,q1=0; clock2 → q0=0,q1=1 (the 1 arrives at q1 one cycle later → correct shift). See the flip-flop model. Units: none, it's logic values.

Example 6 — Register-count trap: which wires become flip-flops? · cell F

wire [15:0] sum  = a + b;         // combinational
wire [15:0] prod = sum * c;       // combinational
reg  [15:0] y;
always @(posedge clk) y <= prod;  // sequential: only THIS latches

Forecast: guess the flip-flop count — 80, 48, or 16?

1. List every named signal. a, b, c (inputs), sum, prod, y. Why? We must decide, per signal, "does this remember across a clock?"
2. Apply the register test to each. A signal becomes a register only if it is assigned inside @(posedge clk). Only y is. Why this tool — the register test? From the synthesis rule in the parent: combinational wire/assign become gates, not memory.
3. Count. sum and prod are pure combinational wires → 0 flip-flops. a,b,c are input ports → not stored here. y is 16 bits → 16 flip-flops. Why the student is wrong: they counted wires as storage; only clocked signals hold state.

Verify: flip-flops $=16$ (only y). The adder + multiplier synthesize as gates (combinational logic), not registers. The claimed 80 is $5\times 16$, off by counting 4 non-registers. Units: flip-flops (bits of state).

Example 7 — The exam twist: two paths, one critical · cell H

Forecast: guess which path is critical for setup, and guess whether the same path matters for hold.

1. Setup uses the SLOWEST path (max $t_{comb}$). P2 at $1.9$ ns is the critical path. Why? Setup fails if any path hasn't settled; the slowest is the binding one.
2. Compute setup demand on P2. $0.2+1.9+0.3=2.4$ ns. Supply $T=2.2$ ns → slack $=2.2-2.4=-0.2$ ns → FAIL by $0.2$ ns. Why? The slow path overruns the whistle.
3. Hold uses the FASTEST path (min $t_{comb}$). The quick route arrives at $t_{cq}+t_{comb,min}=0.2+0.1=0.3$ ns. Why this switch? Setup asks "is the slow one done in time?"; hold asks "does the fast one arrive too soon?" — opposite extremes of the same register pair.
4. Compare to hold. Need $\ge t_{hold}=0.4$ ns; have $0.3$ ns → HOLD FAIL by $0.1$ ns. Why both fail at once: a design can violate setup (slow path) and hold (fast path) simultaneously — they are independent constraints.

Verify: setup demand on P2 $=2.4$ ns, slack $=-0.2$ ns (fail). Hold arrival $=0.3$ ns vs $0.4$ ns → deficit $0.1$ ns (fail). Fix setup by pipelining P2; fix hold by adding $0.1$ ns delay on the fast path. Units ns.

Example 8 — The exact-limit degenerate case (slack = 0) · cell A edge

Forecast: is slack positive, exactly zero, or negative? And is zero slack safe?

1. Demand. $0.3+2.4+0.3=3.0$ ns. Why? Same setup sum.
2. Slack. $3.0-3.0=0.0$ ns — exactly zero. Why this is the boundary: the data becomes steady at the instant $t_{setup}$ before the edge — no earlier.
3. Judge it. Zero slack passes on paper but leaves no margin for temperature, voltage, or aging variation. Why care? Real silicon drifts; a $0$-slack path fails in the field. Designers keep a positive guard band.

Verify: demand $=3.0$ ns $=T$, slack $=0.0$ ns. Passes exactly, zero margin. Units ns.

Related: RTL (register transfer level) design · HDL & Digital Design Flow · Verilog syntax and semantics · Finite State Machines · Clock domains and metastability

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