RTL (register transfer level) design

3.5.6 · Hardware › HDL & Digital Design Flow

HOW data actually flow karta hai? (Timing derive karo)

Worked Example 1 — Ek simple accumulator

Design: acc <= acc + data_in; har clock par.

module accum(input clk, input rst, input [7:0] data_in,
             output reg [7:0] acc);
  always @(posedge clk) begin
    if (rst) acc <= 8'd0;      // synchronous reset
    else     acc <= acc + data_in;
  end
endmodule

Step: <= (non-blocking) use karo. Yeh step kyun? Non-blocking assignment update ko timestep ke end mein schedule karta hai, "saare registers edge par simultaneously latch hote hain" ko model karta hai. Real flip-flops sab ek saath fire hote hain — <= isse match karta hai. Yahan = use karne se ek false ordering dependency create hogi jo hardware mein exist nahi karti.

Step: reset @(posedge clk) ke andar. Kyun? Yeh ek synchronous reset hai — yeh sirf edge par effect leta hai, bilkul us real logic ki tarah jo D input feed karta hai.

Timing: critical path = adder. Agar $t_{c q} = 0.2$ ns, adder $t_{co mb} = 1.5$ ns, $t_{se t u p} = 0.3$ ns, toh $T \geq 2.0$ ns, isliye $f_{ma x} = 500$ MHz.

Worked Example 2 — Combinational vs sequential split

Compute karo y = (a + b) * c, registered output.

reg [15:0] y;
wire [15:0] prod = (a + b) * c;   // combinational (assign-style)
always @(posedge clk) y <= prod;  // sequential: latch it

Step: arithmetic ko combinational rakho, sirf end mein latch karo. Kyun? "Compute" (ek pure function, no clock) ko "store" (register) se alag karna RTL ka essence hai. Tool ek adder + multiplier ko gates ke roop mein synthesize karta hai, phir ek register bank.

Forecast-then-Verify: Predict karo — kitne registers? Sirf 16-bit y → 16 flip-flops. Adder/multiplier gates hain, registers nahi. ✅ (Beginners aksar sochte hain har wire stored hota hai — hota nahi.)

Worked Example 3 — Sequential logic mein blocking mistake

// BUGGY intent: a aur b ko har clock par swap karo
always @(posedge clk) begin
  a = b;   // blocking
  b = a;   // ab b ko NEW a milta hai, purana a nahi!
end

a=b execute hota hai, phir b=a already-updated a dekhta hai. Dono purana b ban jaate hain. Fix:

always @(posedge clk) begin
  a <= b;
  b <= a;   // dono OLD values use karte hain → true swap
end

Fix kyun kaam karta hai: non-blocking saare right-hand sides ko pre-edge values se padhta hai, phir simultaneously update karta hai — ek faithful register model.

Common mistake Steel-manned common mistakes

1. "= use karo sequential blocks mein, yeh simpler hai." Kyun sahi lagta hai: software mein, = normal assignment hai aur order obvious hota hai. Sachai: real flip-flops edge par parallel update hote hain; blocking = ek sequential order impose karta hai jo hardware mein exist nahi karta → simulation-synthesis mismatch aur swap bugs. Fix: sequential (posedge) ke liye <=, combinational (always @(*)) ke liye =.

2. "Main clock raise karke ise faster bana sakta hoon." Kyun sahi lagta hai: faster clocking = zyada kaam/sec. Sachai: agar $T < t_{c q} + t_{co mb} + t_{se t u p}$ , logic settle nahi hua → setup violation → garbage. Fix: pehle critical path chota karo (pipeline karo), phir $f$ raise karo.

3. "Har signal jo main name karta hoon woh register ban jaata hai." Kyun sahi lagta hai: code mein variables values "hold" karte hain. Sachai: sirf woh signals jo @(posedge clk) mein assign hote hain (ya feedback ke saath) registers bante hain; combinational assigns sirf wires/gates hain. Fix: pucho "kya isse clock ke across yaad rakhne ki zaroorat hai?" Agar nahi → combinational.

4. "Slow clock hold violations fix kar deta hai." Kyun sahi lagta hai: slower clock setup fix karta hai, symmetric lagta hai. Sachai: hold constraint $t_{c q} + t_{co mb, min} \geq t_{h o l d}$ mein koi $T$ nahi hai. Fix: short path par delay buffers add karo.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Ek relay race imagine karo. Registers woh runners hain jo fixed spots par khade hain aur ek baton (ek number) pakde hain. Clock ek seeti hai. Har seeti par, har runner baton agle runner ko de deta hai. Lekin seeti ke beech, baton ek choti machine (logic) se guzarti hai jo ise change karti hai — shayad 1 add karti hai. Poori trick yeh hai: machine ko baton change karna agle seeti se pehle khatam karna hoga, warna agle runner ek adha-pakka number pakad leta hai. Seeti bahut fast bajao → chaos. RTL sirf yeh likhna hai: "har seeti par, yeh runner yeh changed baton leta hai."

Flashcards

RTL ka matlab kya hai aur yeh kya describe karta hai?

Register Transfer Level — hardware ko registers (state) plus combinational logic ke roop mein describe karta hai jo har clock edge par unke beech data transfer karta hai.

RTL mein do fundamental building blocks kaun se hain?

Combinational logic (no memory, inputs ka pure function) aur sequential logic (registers jo clock edge par update hote hain).

Max-clock-period (setup) constraint likho.

T \geq t_{c q} + t_{co mb, ma x} + t_{se t u p}

Critical path max frequency kyun determine karta hai?

Yeh registers ke beech sabse slow combinational path hai; clock period iske delay se zyada honi chahiye (plus

t_{c q} + t_{se t u p}

), isliye yeh

f_{ma x}

cap karta hai.

@(posedge clk) blocks mein non-blocking (<=) kyun use karte hain?

Yeh saare flip-flops ko pre-edge values use karke simultaneously latch hone ko model karta hai, jo real parallel register updates se match karta hai; blocking = false ordering impose karta hai.

Hold-time constraint likho aur note karo kya special hai.

t_{c q} + t_{co mb, min} \geq t_{h o l d}

— isme koi

T

nahi hai, isliye clock slow karna hold violations fix nahi kar sakta.

Synthesis mein kaun se signals registers bante hain?

Sirf woh jo clock edge ke under assign hote hain (ya clocks ke across state yaad rakhne ki zaroorat ho); combinational assigns gates/wires bante hain.

Design ko higher clock frequency par run karne ke liye kya karo?

Critical path chota karo (jaise pipeline karo),

t_{co mb, ma x}

reduce karo; phir

f

raise karo.

Synchronous aur asynchronous reset mein fark (RTL)?

Sync reset @(posedge clk) ke andar hota hai aur sirf edge par act karta hai; async reset sensitivity list mein hota hai aur immediately act karta hai.

Connections

HDL & Digital Design Flow
Verilog syntax and semantics
Combinational logic design
Sequential logic and flip-flops
Logic synthesis
Static Timing Analysis
Pipelining
Finite State Machines
Clock domains and metastability

WHY RTL exist karta hai?

WHAT hai RTL, precisely?