A CPU is a fixed datapath: fetch → decode → execute, one (or few) instruction(s) per cycle, reusing the same ALU. An FPGA lets you build a spatial datapath: lay out one physical hardware unit per operation and stream data through them.
Two independent wins:
1. Spatial parallelism. Put N copies of a compute unit on the silicon → do N operations every cycle, no instruction overhead.
2. Deep pipelining (dataflow). Chain operations so a new result exits every clock cycle after the pipeline fills.
What does FPGA stand for and what makes it "field-programmable"?
Field-Programmable Gate Array; you configure it after manufacturing by loading a bitstream that sets its LUTs and interconnect.
What is a LUT and why can it implement any logic function?
A k-input Look-Up Table stores 2^k output bits = a truth table; any boolean function of k inputs is just its truth table, so writing that table makes the LUT be that gate.
Why do FPGAs include hardened DSP slices instead of building multipliers from LUTs?
Multipliers are large and slow in LUTs; hardwiring multiply-accumulate saves area, power, and boosts clock speed.
Give the pipelined throughput formula for M items through S stages.
cycles = S + (M−1); Time = (S+M−1)·T; speedup = MS/(S+M−1) → S as M→∞.
Why can a 250 MHz FPGA beat a 4 GHz CPU?
Throughput = ops/cycle × clock; FPGA does thousands of ops/cycle via spatial parallelism + pipelining, dwarfing the CPU's high clock but few ops/cycle.
What is timing closure and why does it matter?
Ensuring the longest combinational path ≤ clock period; if violated, values aren't stable at the clock edge and the circuit computes wrong results.
When is an FPGA memory-bound rather than compute-bound?
When P ≤ B·I: bandwidth B times arithmetic intensity I limits you; adding compute units won't help — you must raise intensity (e.g. buffer in BRAM).
FPGA vs ASIC — key trade-off?
ASIC is faster/more efficient but fixed and costly to make; FPGA is reprogrammable after fab with near-ASIC efficiency, at lower clock/density.
Latency vs throughput in a pipeline?
Latency = time for the FIRST result (≈S cycles); throughput = rate of results (1/cycle when full). For large M, throughput dominates.
Recall Feynman: explain to a 12-year-old
A normal computer chip is like a single chef who follows a recipe one step at a time, using the same knife over and over. An FPGA is like an empty kitchen full of loose parts — you can bolt them together into an assembly line built exactly for your dish. Once you build the line, a finished plate comes out every second, instead of one chef doing every step for every plate. You can even take the kitchen apart and build a different assembly line tomorrow. That's why it can beat the single chef even though each worker moves a bit slower.
Dekho, CPU ek fixed chip hai — usme ek hi datapath hota hai jo har instruction ko baari-baari process karta hai. FPGA ka idea alag hai: yeh ek "khaali" chip hai jisme laakhon chhote configurable logic blocks (LUTs) aur programmable wires hote hain. Aap Verilog ya HLS me apna circuit likhte ho, aur bitstream load karke chip ko exactly wahi hardware bana dete ho jo aapke algorithm ko chahiye. Matlab problem ko chip pe fit karne ke bajaye, chip ko problem ke shape me dhaal dete ho.
Speed do jagah se aati hai. Ek — spatial parallelism: agar aapko 100 multiply chahiye to 100 multiplier ek saath silicon pe daal do, har cycle me 100 kaam. Do — pipelining: operations ko ek assembly line ki tarah joड़ो, pipeline bharne ke baad har clock cycle me ek naya result bahar. Formula yaad rakho: cycles = S + (M−1), aur speedup = MS/(S+M−1), jo M bada hone par S ke barabar ho jaata hai. Isliye 250 MHz ka FPGA bhi 4 GHz CPU ko haraa sakta hai — kyunki throughput = ops-per-cycle × clock, aur FPGA ek cycle me hazaaron ops karta hai.
Bada exam-trap yeh hai ki log sochte hain "clock kam hai to slow hoga" — galat! Aur "C code recompile karke FPGA pe chala dunga" — bhi galat; aapko loops unroll karna, arrays partition karna, dataflow me sochna padta hai. Aur agar aap memory-bound ho (roofline: P ≤ B·I), to extra compute units bekaar padi rahengi — bottleneck fix karo, BRAM me data buffer karke arithmetic intensity badhao.
Kab use karein? Jab workload streaming/custom ho aur aapko best performance-per-watt aur low latency chahiye — jaise signal processing, network packet processing, ML inference. FPGA GPU aur ASIC ke beech ka sweet spot hai: ASIC jaisi efficiency par reprogrammable.
