Noesis
6.5.11Advanced & Emerging Architectures

RISC-V custom extensions for accelerators

2,035 words9 min readdifficulty · medium
🇮🇳 Yeh note Hinglish mein padho →

WHY does this even exist?

WHY do we want it (the 80/20 core):

  • General-purpose CPUs are flexible but slow for narrow workloads (crypto, AI dot-products, DSP).
  • A dedicated ASIC is fast but rigid.
  • A custom instruction is the sweet spot: reuse the CPU's fetch/decode/registers/memory, but add one hot operation in silicon. You pay area only for the 20% of ops that cause 80% of runtime.

WHAT space is legally yours?

RISC-V opcodes are the low 7 bits of a 32-bit instruction (inst[6:0]). The spec reserves four major opcodes for non-standard use:

You typically shape them like the standard R-type format so existing hardware datapaths (two source registers, one destination) can be reused:

funct7⏟7  rs2⏟5  rs1⏟5  funct3⏟3  rd⏟5  opcode⏟7\underbrace{\text{funct7}}_{7}\;\underbrace{\text{rs2}}_{5}\;\underbrace{\text{rs1}}_{5}\;\underbrace{\text{funct3}}_{3}\;\underbrace{\text{rd}}_{5}\;\underbrace{\text{opcode}}_{7}

HOW is a custom instruction built? (derive the encoding budget)

Derivation from first principles. An R-type instruction has these variable fields that select which operation runs (not the operands): funct3 (3 bits) and funct7 (7 bits). The register fields rs1/rs2/rd choose data, not operation. So:

Nops per slot=2funct3 bits×2funct7 bits=23×27=210=1024N_{\text{ops per slot}} = 2^{\text{funct3 bits}} \times 2^{\text{funct7 bits}} = 2^{3}\times 2^{7}= 2^{10}=1024

With 4 custom slots (custom-0..3):

Ntotal=4×1024=4096 distinct R-type custom instructions.N_{\text{total}} = 4 \times 1024 = 4096 \text{ distinct R-type custom instructions.}

Two ways to attach the accelerator

Steel-manning the classic mistakes

Active recall

Recall Can you answer before revealing?
  • Name the four reserved custom opcodes and why they're safe.
  • Why R-type is the natural template for a custom instruction.
  • Derive how many custom R-type ops fit in one opcode slot.
  • When do you pick a loosely-coupled coprocessor over a tightly-coupled unit?
  • Steel-man: why "more custom instructions = more speed" is wrong.
Recall Feynman: explain to a 12-year-old

Imagine a chef (the CPU) who can follow any recipe but slowly. RISC-V leaves a few blank recipe cards in the cookbook. You're allowed to write your own super-recipe on a blank card — say "make 100 sandwiches at once" — and build a special machine in the kitchen that does exactly that. Now when the chef reads that card, one word triggers the machine and lunch is ready in a flash. Other chefs using the normal cookbook aren't confused, because they never read your blank cards.

Connections

Which opcode bits identify a RISC-V instruction?
The low 7 bits, inst[6:0].
Which four opcodes does RISC-V reserve for custom/non-standard use?
custom-0 0001011, custom-1 0101011, custom-2 1011011, custom-3 1111011.
Why are custom instructions safe from colliding with future standards?
The spec guarantees ratified extensions will never use the reserved custom opcode space.
Why is R-type the natural format for a custom instruction?
The register file already provides two read ports (rs1,rs2) and one write port (rd), so decode/forwarding is reused; funct3+funct7 give free operation-select bits.
How many distinct R-type custom ops fit in one opcode slot?
2^3 (funct3) × 2^7 (funct7) = 1024.
How many total across all four custom slots?
4 × 1024 = 4096.
Tightly-coupled vs loosely-coupled accelerator — key difference?
Tight sits in the pipeline (register operands, low latency); loose (e.g. RoCC) is a coprocessor with its own memory/DMA for large streaming data.
Why not just attach the accelerator via MMIO?
MMIO round-trips cost hundreds of cycles, destroying gains for fine-grained ops; custom instructions avoid that overhead.
Steel-man fix: "more custom instructions = more speed"?
Benefit = op-frequency × cycles-saved − area/verification cost; only harden the profiled hot kernel (80/20), or you waste silicon.
What happens if a core without your custom instruction executes it?
It traps (illegal instruction) — no silent wrong result, so standard binaries stay safe.

Concept Map

reserves

defines

triggers

flexible but slow

fast but rigid

solved by

shaped as

reuses

selects op via

gives

beats

costs

operands from registers

RISC-V base ISA

Custom opcode space

Custom extension

Tightly coupled accelerator

General-purpose CPU

Need for speed

Dedicated ASIC

R-type format

Register file 2 read 1 write

funct3 and funct7

Encoding budget 2^10 sub-ops

Off-chip MMIO device

Hundreds of cycles latency

Few-cycle latency

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, normal CPU har kaam kar leta hai lekin kuch specific kaam (jaise AI ka dot-product, crypto, DSP) me slow hota hai. RISC-V ka mast feature ye hai ki wo ISA me kuch khaali opcode slots chhod deta hai — custom-0 se custom-3. In slots me tum apni khud ki instruction define kar sakte ho jo seedha tumhare banaye hue hardware accelerator ko chala de. Aur best baat: kisi vendor se permission lene ki zaroorat nahi, aur existing software bhi nahi tootega.

Format ki baat karein to hum aam taur pe R-type shape use karte hain: funct7, rs2, rs1, funct3, rd, opcode. Kyun? Kyunki register file me pehle se do read port aur ek write port hote hain, to decode/forwarding logic reuse ho jaata hai. funct3 (3 bit) aur funct7 (7 bit) mila ke 210=10242^{10}=1024 alag ops ek slot me, aur 4 slots => 4096 custom instructions. Operands registers se aate hain, result register me wapas — sirf kuch cycles ki latency. Isiliye ye MMIO device se kahin behtar hai, kyunki MMIO me har baar sau-sau cycles bus par barbaad hote hain.

Do tarah se accelerator jodte hain: tightly-coupled (pipeline ke andar, chhota data, fast) aur loosely-coupled jaise RoCC coprocessor (apni memory/DMA, bade buffer ke liye). Yaad rakho — "more custom instructions = more speed" galat soch hai. Pehle profile karo (80/20 rule), sirf hot kernel ko hardware me daalo, warna silicon aur verification barbaad. Design flow yaad rakhne ke liye: Profile, Pick, Pack, Plumb, Prove.

Go deeper — visual, from zero

D1FoundationsEvery symbol from zero · 1,929 wordsD2Visual walkthroughThe derivation in pictures · 1,990 wordsD3Worked examplesEvery scenario covered · 3,219 wordsD4ExercisesGraded, full solutions · 2,670 wordsD5Question bankConcept traps, quick reveals · 1,367 words

Test yourself — Advanced & Emerging Architectures

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Connections

ISA (Instruction Set Architecture) — RISC vs CISCCoding · 4.1.3RISC-V base ISA (RV32I - RV64I)Hardware · 5.1.7Amdahl's Law and Gustafson's LawHardware · 6.1.3Memory-mapped filesCoding · 4.2.30Domain-specific acceleratorsHardware · 6.5.6