Ek CPU ek fixed datapath hai: fetch → decode → execute, ek (ya thode) instruction(s) per cycle, wohi ALU baar baar use hota hai. FPGA aapko ek spatial datapath banane deta hai: har operation ke liye ek physical hardware unit lagao aur data unke through stream karo.
Do independent wins:
1. Spatial parallelism. Silicon pe ek compute unit ke N copies lagao → har cycle mein N operations karo, koi instruction overhead nahi.
2. Deep pipelining (dataflow). Operations ko chain karo taaki pipeline fill hone ke baad har clock cycle mein ek naya result nikle.
FPGA ka full form kya hai aur ise "field-programmable" kya banata hai?
Field-Programmable Gate Array; aap ise manufacturing ke baad configure karte ho ek bitstream load karke jo uske LUTs aur interconnect set karta hai.
LUT kya hota hai aur woh koi bhi logic function kyun implement kar sakta hai?
Ek k-input Look-Up Table 2^k output bits store karta hai = ek truth table; k inputs ki koi bhi boolean function bas uski truth table hai, toh woh table likhne se LUT woh gate ban jaata hai.
FPGAs mein LUTs se multipliers build karne ki jagah hardened DSP slices kyun hote hain?
Multipliers LUTs mein bade aur slow hote hain; multiply-accumulate ko hardwire karne se area, power bachti hai aur clock speed badhti hai.
M items ke liye S stages mein pipelined throughput formula batao.
cycles = S + (M−1); Time = (S+M−1)·T; speedup = MS/(S+M−1) → S as M→∞.
250 MHz FPGA 4 GHz CPU ko kyun beat kar sakta hai?
Throughput = ops/cycle × clock; FPGA spatial parallelism + pipelining se hazaron ops/cycle karta hai, CPU ke high clock lekin few ops/cycle ko dwarfing karta hai.
Timing closure kya hai aur yeh kyun matter karta hai?
Yeh ensure karna ki longest combinational path ≤ clock period hai; agar violate ho, toh values clock edge pe stable nahi hoti aur circuit galat results compute karta hai.
FPGA memory-bound kab hota hai compute-bound ki jagah?
Jab P ≤ B·I: bandwidth B times arithmetic intensity I aapko limit karta hai; compute units add karna help nahi karega — intensity badhani hogi (e.g. BRAM mein buffer karo).
FPGA vs ASIC — key trade-off?
ASIC faster/more efficient hai lekin fixed aur banane mein costly hai; FPGA fab ke baad reprogrammable hai near-ASIC efficiency ke saath, lower clock/density pe.
Pipeline mein latency vs throughput?
Latency = PEHLE result ka time (≈S cycles); throughput = results ki rate (1/cycle jab full ho). Bade M ke liye, throughput dominate karta hai.
Recall Feynman: 12-saal ke bachche ko samjhao
Ek normal computer chip ek single chef ki tarah hai jo ek recipe ek step ek time pe follow karta hai, wohi chhaaki baar baar use karta hai. Ek FPGA ek khali kitchen full of loose parts ki tarah hai — aap unhe ek assembly line mein bolt kar sakte ho jo exactly aapki dish ke liye bani ho. Jab line ban jaaye, har second ek finished plate nikalti hai, ek chef ki jagah jo har plate ke liye har step karta hai. Aap kitchen tod ke kal ek alag assembly line bhi bana sakte ho. Isi liye yeh single chef ko beat kar sakta hai chahe har worker thoda slow chale.
