Verilog - VHDL syntax basics: Foundations — Hardware deep dive

Before you can read a single line of the parent note, you need to recognise the raw pieces it throws at you: what a wire is, what a bit is, what &, [7:0], 8'hA5, posedge, <=, assign, always, module each mean and look like — in both Verilog and VHDL. This page builds every one of them from nothing.

0. The most basic object: a wire carrying a bit

Reading the figure: four horizontal lines, each one is a single wire drawn on the board. The top pale-yellow line is held high (1); the blue line below it is low (0). The pink line is x — the simulator drew it as a "muddy" line because it does not know the value. The dashed off-white line is z — dashed because nobody is driving it, so it is floating and electrically invisible. The little arrow reminds you that on real silicon only the top two ever occur; x/z are simulation bookkeeping. Keep this picture — every symbol below is built out of these lines.

See Number Systems and Bit-Widths for how many bits make numbers.

1. A bus: many bits bundled — the `[7:0]` notation

Reading wire [7:0] bus; from the parent note out loud:

wire — "this is a bundle of plain wires (no memory)."
[7:0] — "the index of the top wire is 7, the bottom is 0" — so there are $7 - 0 + 1 = 8$ wires.
bus — the name we gave the bundle.

Reading the figure: eight boxes stand in a row — each box is one wire of the bus. Above each box is its index (7 on the far left down to 0 on the far right); below it is its place value $2^{index}$ . The wires carrying 1 are drawn yellow, the 0 wires blue, so the pattern 10100101 is visible at a glance. The pink arrows label the leftmost box as the MSB (worth 128) and the rightmost as the LSB (worth 1). Add up only the yellow boxes — $128 + 32 + 4 + 1$ — and you get 165, which the caption confirms equals 8'hA5. This single picture ties together the bus, MSB/LSB, place values, and the hex literal.

1b. Indexing and slicing — pulling wires back out

Reading the figure: the same 8-wire ribbon from before. A pink bracket wraps boxes 7–4 and is labelled bus[7:4] — a part-select that pulls those four wires off as a smaller 4-wire ribbon (drawn peeling away to the right). A separate blue arrow points at the single box 3, labelled bus[3] — a bit-select that taps exactly one wire. Notice the untouched wires just continue straight: slicing does not copy or compute, it simply routes a chosen subset of physical lines onward.

2. Reading a bus as a number — bases `b o d h`

2b. The two extra wire states: `x` and `z`

3. The literal notation `8'hA5` — width ' base value

So 4'b1010 = "4 wires, binary, value 1010" and 8'hA5 = "8 wires, hex, value A5". Every literal states its width because — again — a constant has to fit onto a fixed number of physical lines.

3b. Signed vs unsigned literals

4. Concatenation `{ , }` — gluing buses side by side

{4'b1010, 4'b0101} places 1010 in the top 4 wires and 0101 in the bottom 4, producing the 8-bit 10100101 — the same 165 as 8'hA5. The picture: two 4-wire ribbons taped end to end into one 8-wire ribbon.

5. The operator zoo — `&` `|` `~` `^` and the logical twins

Reading the figure: three standard gate outlines drawn in chalk. The flat-backed bullet is AND (&), the curved-back shield is OR (|), and the double-curved shield with the extra tail is XOR (^). Each has two wires coming in from the left (the fan-in: the inputs a and b) and one wire leaving to the right (the fan-out: the output y). The truth beneath each gate reminds you when the output goes high. This is what a bitwise operator becomes — a soldered shape, not a calculation.

5b. The `assign` keyword — drawing a permanent wire

Definition

assign (continuous assignment) ==assign== is the Verilog keyword that creates a continuous (always-live) connection. The full form is

assign y = a & b;

Read it as: "let the wire y forever equal the AND of a and b." There is no "run once" — the moment a or b changes, y re-evaluates by itself.

assign — the keyword announcing a continuous connection.
y — the left-hand side: the wire being driven (must be a wire, never a reg).
= — here it means "is permanently equal to."
a & b — the right-hand side: the logic that feeds y.

6. Time enters: the clock, `posedge` / `negedge`, and multi-event lists

Reading the figure: the top trace is the clock wire drawn as a square wave — flat low, jump up, flat high, jump down, repeat. Each rising jump is circled and labelled posedge (in blue); each falling jump is circled and labelled negedge (in pink). The flat stretches between edges carry no update — only the circled instants do. That is the whole idea of an edge: not the level, but the moment of change.

Definition

always — the procedural block ==always== is a Verilog keyword that starts a procedural block: a chunk of statements that re-executes every time one of the events it is "sensitive" to occurs. It is the opposite of assign: instead of one permanent equation, it is a "whenever this happens, do these steps" recipe.

always @(EVENTS) begin
    ... statements ...
end

always — "keep re-running this block, forever, on the listed events."
@(EVENTS) — the sensitivity list: which events wake the block (§9).
begin ... end — brackets that group the statements inside (like { } in C). With @(*) it builds combinational logic; with @(posedge clk) it builds clocked memory. (There is also initial, a block that runs once at time zero — used only in Testbenches, never in synthesizable hardware.)

6b. The full clocked block — `always @(posedge clk)` with `if`/`else`

Definition Multi-event sensitivity:

@(posedge clk or negedge rst) You can list several edges joined by ==or==. The classic pattern

always @(posedge clk or negedge rst) begin
    if (!rst)  q <= 1'b0;   // rst dropping to 0 clears immediately
    else       q <= d;      // otherwise update on the clock edge
end

This is an asynchronous reset: the block wakes on either a clock rise or the reset falling, so the register can be cleared without waiting for the clock. Here if (!rst) uses the logical-NOT ! from §5 — "if reset is not high (i.e. it just went low)."

7. `reg` vs `wire` — does it hold a value?

8. The two "="s — `=` and `<=` (the heart, previewed)

You do not need to master these yet — the parent note dedicates its whole core section to them. Here just anchor the symbols: <= looks like the up-arrow of an edge, = is the plain instant-equals. The distinction matters because Synthesis vs Simulation can disagree if you pick wrong.

8b. The ternary operator `? :` — one-line mux

9. `@(*)` — the sensitivity list

10. The container: `module` / `endmodule` and the port list

Definition

module and endmodule ==module opens the basic reusable block; endmodule== closes it. Everything describing one piece of hardware lives between them.

module and2 (input a, input b, output y);  // name + port list
    assign y = a & b;
endmodule

module — keyword starting the block.
and2 — the block's chosen name.
( ... ) — the port list: the legs of the chip.
endmodule — keyword ending the block (no semicolon after it).

Definition inout and tri-state

An ==inout== port can be both driven and read. To share one physical wire among several drivers, each driver must be able to let go — drive z (high-impedance) when it is not its turn:

assign bus = enable ? data_out : 8'bz;  // drive data, or release to z

Here the ? : from §8b picks data_out when enable is high, or 8'bz (all-eight-wires-floating) when it is low — i.e. "let go of the bus."

12. The VHDL half — the same ideas, different words

Everything above was mostly Verilog spelling. VHDL says the same hardware things with different punctuation. Here is the full minimal vocabulary.

Definition entity + architecture (VHDL's module)

==entity== declares the interface: the block's name and its ports (the legs of the chip). It is the VHDL half of Verilog's module header.
==architecture== declares the behaviour: what happens inside — the VHDL half of the module body.

entity and2 is
    port ( a, b : in  std_logic;      -- input ports
           y    : out std_logic );    -- output port
end and2;
architecture rtl of and2 is
begin
    y <= a and b;                     -- concurrent signal assignment
end rtl;

port ( … ) lists ports; each has a direction (in/out/inout) and a type (std_logic = one four-state wire, std_logic_vector(7 downto 0) = an 8-bit bus). The concurrent <= here is VHDL's version of Verilog's assign.

Definition process, if/then/else, rising_edge (VHDL's always)

process (clk)                 -- sensitivity list in parentheses
begin
    if rising_edge(clk) then  -- VHDL's posedge
        if rst = '1' then     -- VHDL if uses 'then', closes with 'end if'
            q <= '0';
        else
            q <= d;
        end if;
    end if;
end process;

==process== = VHDL's always block.
==rising_edge(clk)== = posedge clk; falling_edge(clk) = negedge clk.
VHDL's ==if … then … else … end if== is the same conditional as Verilog's if/else, just with the words then and end if.

Definition Instantiation, port map, generics

To use a block inside another, you instantiate it and connect its ports with a ==port map==:

U1 : and2 port map ( a => x, b => y, y => z );  -- name => wire

A ==generic== is a compile-time parameter (e.g. a bus width N) — VHDL's version of Verilog parameter. It lets one description build many sizes.

Recall Verilog ↔ VHDL cheat-map

Verilog module ::: VHDL entity + architecture Verilog assign y = ... ::: VHDL concurrent y <= ... Verilog [7:0] ::: VHDL (7 downto 0) Verilog & | ~ ^ (gates) ::: VHDL words and or not xor