Verilog - VHDL syntax basics: Visual walkthrough — Hardware deep dive

We build the whole idea around one tiny, famous circuit: swapping the contents of two registers on a clock edge. It is the smallest program where = and <= give different hardware, so it is the perfect microscope.

Step 1 — What is a "wire" vs a "box"? (the two atoms)

WHAT we set up: two boxes, named $a$ and $b$ , each holding one bit. WHY: everything about <= vs = is about when a box captures its new value. To talk about "when", we need boxes (things with memory) and a clock (the thing that says "now"). PICTURE: below, the blue lines are wires (instant), the yellow squares are registers (memory). The red sawtooth at the bottom is the clock — a signal that marches $0, 1, 0, 1, \dots$ forever.

Here $a$ and $b$ are the two register boxes. See Flip-Flops and Latches for what one box is made of — for now, "box = remembers one bit until the clock says update."

Step 2 — What does "the clock edge" mean? (the instant of update)

WHAT: we mark the exact instants where boxes are allowed to change. WHY: outside those instants, the boxes are frozen. So the whole question "does the swap work?" reduces to: at one edge, what value does each box grab? Nothing else matters. PICTURE: the red clock line has upward arrows at each rising edge. Between edges (the grey bands) every box holds still — its value is a flat plateau.

the trigger posedge clk \Rightarrow the action every box samples now

$posedge clk$ — the event "clock just rose to 1". This is the only moment updates happen.
"every box samples now" — all boxes look at their inputs simultaneously. Hold onto that word simultaneously; it is the whole plot.

Step 3 — The blocking `=` model: a to-do list read top-to-bottom

WHAT: run the swap with blocking assignment.

always @(posedge clk) begin
    a = b;   // line 1
    b = a;   // line 2
end

WHY this is the wrong tool here: blocking behaves like ordinary software — line 1 finishes before line 2 starts. We are about to watch that ordering destroy the swap. PICTURE: trace it as a to-do list with a moving pointer. Suppose before the edge $a = 3$ , $b = 7$ .

line 1: a = b \Rightarrow a := 7 line 2: b = a \Rightarrow b := already overwritten! 7

$a := 7$ — line 1 immediately stamps $b$ 's value (7) into $a$ . The old $a = 3$ is gone.
$b := 7$ — line 2 reads $a$ , but $a$ is now $7$ , not the original $3$ . So $b$ copies $7$ .
Result: $a = 7, b = 7$ . Both became $b$ . The 3 vanished. This is not a swap — it is a copy. It also secretly built a shift, not a swap. This is the "accidental shift-register bug" the parent warned about; see Synthesis vs Simulation.

Step 4 — The non-blocking `<=` model: read everything first, then write everything

WHAT: run the same swap with non-blocking.

always @(posedge clk) begin
    a <= b;   // sample b (old)
    b <= a;   // sample a (old)
end

WHY this is the right tool: real flip-flops sharing one clock all capture their inputs at the same instant (Step 2). Non-blocking's "read-all-then-write-all" is the exact software mirror of that physical simultaneity. PICTURE: split time into two phases at the edge — a read phase (grab old values into a holding pen) and a write phase (commit them all).

read phase: OLD values RHS_{a} = b_{old} = 7, RHS_{b} = a_{old} = 3 ⟶ write phase: commit together a := 7, b := 3

$b_{old} = 7, a_{old} = 3$ — both right sides are read before anything is written, so both see the original values.
$a := 7, b := 3$ — now commit. $a$ gets old- $b$ , $b$ gets old- $a$ .
Result: $a = 7, b = 3$ . A genuine swap. The order of the two lines no longer matters — swap them and you get the same answer.

Step 5 — Side-by-side: the same edge, two universes

WHAT: overlay both waveforms across three clock edges starting from $a = 3, b = 7$ . WHY: to prove the divergence isn't a one-time fluke — the two models drift into different behaviours edge after edge. PICTURE: top pair is the = world (both collapse to 7 and stay), bottom pair is the <= world (values ping-pong / swap each edge).

Step 6 — The degenerate cases (never leave the reader stranded)

WHAT / WHY / PICTURE: four corner cases, each on its own tile of the figure.

$a = b$ already (say both 5). Swap of equal values is invisible: = and <= both leave $5, 5$ . So this case cannot distinguish the two operators — never test your understanding on equal inputs.
Self-assign a <= a;. Read old $a$ , write it back → the box holds. This is how you say "keep the value this cycle" — a deliberate no-change, not a bug.
No assignment on some path (missing else). If a combinational output is left unassigned on a branch, the tool must remember the old value → it infers an unwanted latch (see Flip-Flops and Latches). For clocked <= logic, an unassigned register simply holds, which is fine and intended.
The first edge (power-on, value unknown = $x$ ). Before any reset, a register holds an unknown value, written $x$ . A swap of $x$ and $7$ gives $7$ and $x$ — the unknown propagates until a reset defines it. This is why we add synchronous reset (if (rst) q <= 0;).

no reset \Rightarrow a, b \in {x} first useful edge defined only after r s t

$x$ — Verilog's symbol for "unknown / not yet initialised". Not 0, not 1 — a genuine question mark on the wire.

The one-picture summary

This compresses everything: one clock edge splits into read then write. Feed the same $a = 3, b = 7$ into both models. The = path chains (arrow through line 1 into line 2) and both boxes land on 7. The <= path forks (both reads from old values) and the boxes truly swap to $7, 3$ . The clock at the bottom reminds you: all of this happens at one rising edge, and between edges everything is frozen.

Recall Feynman: the whole walkthrough in plain words

Picture two lockers, $a$ with a 3 inside and $b$ with a 7. A bell rings once (the clock edge) and you want the numbers to trade places. If you use = you're being hasty: you open locker $a$ , dump 7 in — but now the original 3 is thrown away, so when you go to fill $b$ you only find 7 to copy. Both lockers end up 7. The 3 is lost forever. If instead you use <=, you first stand back and read both lockers onto a notepad (a=3, b=7) before touching anything. Then, in one motion, you write the notepad values into the opposite lockers. Now they truly swap: $7$ and $3$ . That "read everybody first, then write everybody" is precisely how real flip-flops behave — when the bell rings, every memory box glances at its input at the very same instant, then flips together. So: bell/clock → <= (wait, read all, swap together); plain wire → = (do it now). And beware the corners: equal values hide the difference, unassigned combinational paths accidentally grow a memory latch, and before a reset everything is a big unknown $x$ .

Connections

Verilog - VHDL syntax basics — the parent; this page derives its golden rule.
Combinational vs Sequential Logic — the two worlds = and <= live in.
Flip-Flops and Latches — the "box" of Step 1, and the inferred latch of Step 6.
Synthesis vs Simulation — where the =-in-clock bug bites hardest.
Finite State Machines in HDL — uses both styles together.
Number Systems and Bit-Widths — the values inside the boxes.
Testbenches — where you'd actually watch these waveforms.
Hinglish version →