Exercises — Verilog - VHDL syntax basics

The clue is what triggers the update.

1. assign = continuous — y re-evaluates the instant a or b changes. Combinational. (^ is XOR: 1 when the two bits differ.)
2. always @(posedge clk) fires only on a rising clock edge, and stores d into q until the next edge; <= marks it as a register update. Sequential.
3. always @(*) re-runs whenever any right-hand-side input changes, with no clock, so y tracks a & b (AND) continuously. Combinational.

Rule map: assign and always @(*) → combinational; always @(posedge clk) → sequential. See Combinational vs Sequential Logic.

Apply the Golden Rule: clocked → <=, combinational → =.

1. This is posedge clk (clocked) → <= (non-blocking).
2. This is always @(*) (combinational) → = (blocking).

Mnemonic from the parent: the arrow <= "waits for the edge"; plain = "equals now."

The prefix 4'h means 4 bits wide, base hexadecimal. The hex digit C = binary 1100.

• Binary 1100 = $1\cdot 8+1\cdot 4+0\cdot 2+0\cdot 1=12$.
• Value = 12, and it drives 4 wires (one physical line per bit). See Number Systems and Bit-Widths.

Concatenation {high, low} glues bit-groups left-to-right, high bits first.

• High nibble 1100, low nibble 0011 → 11000011.
• Group into hex: 1100 = C, 0011 = 3 → 8'hC3.
• Check decimal: $11000011_2=128+64+2+1=195$, and `0xC3 = 12\cdot16 + 3 = 195$. ✓

Verilog (& = AND):

module and4 (input a, input b, input c, input d, output y);
    assign y = a & b & c & d;   // continuous → combinational
endmodule

VHDL (the interface is the entity, the behaviour is the architecture; and is the keyword, and <= here is a concurrent signal assignment, not a clocked one):

entity and4 is
    port ( a, b, c, d : in  std_logic;
           y          : out std_logic );
end and4;
architecture rtl of and4 is
begin
    y <= a and b and c and d;   -- concurrent → combinational
end rtl;

Why assign / concurrent <=? There is no memory and no clock — y must always equal the AND of the four inputs, instantly. Both forms create a permanent wire relationship.

Verilog:

module dff (input clk, input rst, input d, output reg q);
    always @(posedge clk) begin   // synchronous → sample only on clock edge
        if (rst) q <= 1'b0;       // clocked → non-blocking
        else     q <= d;
    end
endmodule

The same flip-flop in VHDL (a process plays the role of always; rising_edge(clk) is posedge clk):

entity dff is
    port ( clk, rst, d : in  std_logic;
           q           : out std_logic );
end dff;
architecture rtl of dff is
begin
    process (clk) begin
        if rising_edge(clk) then      -- synchronous
            if rst = '1' then q <= '0';
            else              q <= d;
            end if;
        end if;
    end process;
end rtl;

Why posedge clk / rising_edge(clk)? Synchronous reset means the reset only acts at the clock edge, so rst lives inside the clocked block. Why <=? Clocked storage → non-blocking. See Flip-Flops and Latches.

Block A (=, blocking): lines execute in order, updating immediately.

• a = b; → a becomes 0.
• b = a; → reads the new a (which is now 0) → b becomes 0.
• Result: a=0, b=0 — the swap is destroyed, a was clobbered.

Block B (<=, non-blocking): all right-hand sides are sampled first (using old values), then all left-hand sides update together.

• RHS sampled: b=0, a=1 (old values).
• Then assign: a<=0, b<=1.
• Result: a=0, b=1 — a genuine swap. ✓

This is why real flip-flops need <=: on one edge every register grabs its input simultaneously. See Synthesis vs Simulation.

Non-blocking → all RHS sampled from old values first:

• old a=1, old b=0.
• Then: b <= 1, c <= 0.
• a is not assigned here, so it keeps 1.
• Result: a=1, b=1, c=0.

Notice c got the old b (0), not the new one. This is the correct shift-register behaviour: on each edge the "wave" moves one stage. Had this been blocking =, b would update to 1 first and c would also grab 1 — collapsing two stages into one edge (a classic bug).

Yes — it infers a latch. In a combinational block, every output must be assigned on every path.

• When sel = 1: y = a. Fine.
• When sel = 0: y is never assigned → the tool must remember the previous y → it builds a latch (memory you didn't ask for).
• So the old value is held whenever sel = 0.

The figure below traces exactly this decision: follow the two branches out of if (sel) and watch which one fails to drive y.

Fix: give a default, e.g. y = 1'b0; before the if, or add an else y = ...;. Then y is defined on all paths and stays purely combinational.

Every path must assign y, so we use a complete if/else (or a default).

module mux2 (input a, input b, input sel, output reg y);
    always @(*) begin
        if (sel) y = b;   // sel = 1
        else     y = a;   // sel = 0  → every path assigns y
    end
endmodule

Why =? always @(*) is combinational → blocking. Why complete if/else? Both branches drive y, so no old value is ever remembered → no latch. (A one-liner assign y = sel ? b : a; works too and is even cleaner.)

module counter4 (input clk, input rst, output reg [3:0] count);
    always @(posedge clk) begin
        if (rst) count <= 4'd0;      // clocked → non-blocking
        else     count <= count + 1;
    end
endmodule

[3:0] declares a 4-bit vector (bit 3 = MSB). Wrap-around: 4 bits hold values 0–15. After 4'hF (= 15 = 1111), adding 1 overflows to 10000, but only the low 4 bits are kept → 0000. So 4'hF is followed by 4'h0 — the counter naturally wraps every 16 edges. See Number Systems and Bit-Widths.

module add_reg (input clk, input [3:0] x, input [3:0] y, output reg [4:0] s);
    always @(posedge clk) begin
        s <= x + y;   // clocked → non-blocking; 5-bit result holds carry
    end
endmodule

Why 5 bits? Two 4-bit numbers max out at $15+15=30$, which needs $\lceil {\log }_{2}31\rceil =5$ bits (11110). A 4-bit output would drop the carry and give a wrong sum on overflow. Why <=? The result is stored on the edge → sequential → non-blocking.

Simulation with <= in a combinational block: RHS are sampled from old values, so:

• t <= a → schedules t = 1, but reads old t = 0 for the next line.
• y <= t → uses old t = 0 → y gets 0 this pass.
• The block re-triggers when t changes to 1, and only then does y become 1 — one delta-cycle late. So in simulation y needs two evaluation passes to reach 1 (it lags behind a).

What synthesis builds: the tool ignores the delta-timing and wires y = a directly (pure combinational path). So hardware gives y = 1 immediately, but simulation showed a delay.

That gap — sim behaves one way, silicon another — is the dreaded simulation/synthesis mismatch. Fix: use blocking = in combinational blocks so simulation matches the wire the tool actually builds. See Synthesis vs Simulation.

Blocking = updates immediately, in order:

• q3 = q2; → q3 = 0 (old q2).
• q2 = q1; → q2 = 1 (old q1).
• q1 = d; → q1 = 0.
• Result: q1=0, q2=1, q3=0.

Here it happens to look correct — because the order (q3 first, then q2, then q1) reads the still-old value before it's overwritten. But reverse the order (q1=d; q2=q1; q3=q2;) and every stage grabs the just-written value → d races through all three flip-flops in one edge → the shift register collapses to a single stage.

Lesson: blocking makes correctness depend on line order — fragile and non-obvious. Non-blocking <= samples all old values first, so the shift is always exactly one stage regardless of order. Always use <= in clocked blocks.

The sensitivity list decides when the block wakes up.

• DFF-A wakes only on posedge clk. So rst is examined only at the clock edge → synchronous reset. If rst pulses between edges, q does not change until the next rising clock. (b) → waits for the next edge.
• DFF-B also wakes on posedge rst. So a rising rst fires the block immediately, independent of the clock → asynchronous reset. (b) → q goes to 0 immediately.

Why it matters: async reset clears instantly (good for power-up safety) but its release must be handled carefully to avoid metastability; sync reset is simpler and cleaner in timing but can't clear a stuck clock. Both are valid — the sensitivity list is your explicit declaration of which you built. See Flip-Flops and Latches.

Golden Rule ::: Clocked always @(posedge clk) → <=; combinational always @(*) → =, and assign every output on every path. Sum of two $n$-bit numbers needs how many bits? ::: $n+1$ (to hold the carry-out). 4'hF + 1 in a 4-bit counter → ::: 4'h0 (wraps around, mod 16).