Verilog - VHDL syntax basics — Hinglish notes

3.5.1 · Hardware › HDL & Digital Design Flow

WHAT: ek HDL kya describe karta hai?

HOW: do core assignment types (iska dil)

Minimal complete examples

Worked example 2-input AND (combinational, dataflow)

Verilog

module and2 (input  a, input  b, output y);
    assign y = a & b;   // continuous: y always equals a AND b
endmodule

VHDL

entity and2 is
    port ( a, b : in  std_logic;
           y    : out std_logic );
end and2;
architecture rtl of and2 is
begin
    y <= a and b;       -- concurrent signal assignment
end rtl;

Yeh step kyun? assign / concurrent <= ek permanent relationship banata hai — jis moment a ya b change hota hai, y re-evaluate ho jaata hai. Yeh exactly ek AND gate se guzarne wali wire hai.

Worked example D flip-flop (sequential, behavioural)

module dff (input clk, input rst, input d, output reg q);
    always @(posedge clk) begin   // fires only on rising clock edge
        if (rst) q <= 1'b0;       // synchronous reset
        else     q <= d;          // NON-blocking: models the register
    end
endmodule

output reg q kyun? always ke andar assign hone wale signal ko reg declare karna padta hai (yeh events ke beech value hold karta hai). <= kyun? Taaki agar kaafi saare registers ek doosre ko reference karein, toh sabhi ek saath purani values sample karein — jaise real flip-flops ek clock share karte hain.

Worked example Do registers swap karna (dikhata hai

<= kyun matter karta hai)

always @(posedge clk) begin
    a <= b;
    b <= a;   // both RHS read FIRST → genuine swap
end

Blocking = se, line 1 a ko overwrite kar deti, toh line 2 naye a ko copy karti aur dono b ban jaate. Yeh step kyun? Non-blocking hardware ki parallel nature ko capture karta hai: ek edge par, har flip-flop apna input value ek saath grab karta hai.

Worked example Bus, literal, aur concatenation syntax

wire [7:0] bus;          // 8-bit vector, bit 7 = MSB
assign bus = 8'hA5;      // 8-bit hex literal = 10100101
assign bus = {4'b1010, 4'b0101};  // concatenation {high, low}

Width prefix 8'h kyun? HDL mein har literal ki explicit bit-width aur base hoti hai (b,o,d,h) kyunki hardware wires mein physical lines ki ek fixed number hoti hai.

Common mistakes (Steel-man + fix)

Flashcards

Verilog module vs VHDL entity/architecture kya hai?

module interface + behaviour ko ek saath bundle karta hai; VHDL interface (entity, ports) ko internal behaviour (architecture) se alag karta hai.

always @(*) mein combinational logic ke liye kaunsa assignment type use karein?

Blocking =.

always @(posedge clk) ke andar kaunsa assignment type use karein?

Non-blocking <=.

Non-blocking <= flip-flops ko sahi se model kyun karta hai?

Pehle saare right-hand sides sample hote hain, phir saare left-hand sides ek saath update hote hain — yeh parallel edge-triggered registers se match karta hai.

Verilog mein continuous combinational connection kya banata hai?

assign y = f(inputs); (continuous assignment).

always block mein drive hone wale signal ko reg kyun hona chahiye?

Use events ke beech apni value hold karni hoti hai; reg Verilog mein ek variable-type storage hai.

8'hA5 ka matlab kya hai?

Hexadecimal mein ek 8-bit-wide literal, value 10100101.

Inferred latch kya hai aur use kaise avoid karein?

Ek memory element jo tab create hoti hai jab ek combinational output har path par assign nahi hoti; har branch mein saare outputs ko default/assign karke avoid karo.

Kya do alag assign statements ordered hain?

Nahi — yeh concurrent hardware hain, page par order irrelevant hai.

{4'b1010, 4'b0101} kya produce karta hai?

Concatenation → 8-bit value 10100101.

Recall Feynman: ek 12-saal ke bacche ko explain karo

Socho tum ek robot builder ko sirf text mein ek machine describe kar rahe ho. Tum keh sakte ho "yeh wire hamesha inhi do buttons ka AND hai" — woh wire kabhi nahi soti, instantly react karti hai (yeh hai assign). Ya tum keh sakte ho "har baar jab ghanti bajti hai, is wire par jo hai use yaad karo" — yeh ek memory box hai jo sirf ghanti (clock edge) par update hoti hai. Tricky part yeh hai: jab ghanti bajti hai, saare memory boxes ek hi instant mein apne inputs dekhte hain aur phir sab ek saath flip ho jaate hain — isliye hum <= likhte hain matlab "sablog, abhi apni value lo, aur ek saath swap karo," = ki jagah jo matlab hai "yeh abhi karo agle line se pehle."

Connections

Combinational vs Sequential Logic — woh do behaviours jinhe HDL styles map karte hain.
Flip-Flops and Latches — always @(posedge clk) kya synthesize karta hai.
Synthesis vs Simulation — blocking/non-blocking choice mismatches kyun paida karti hai.
Finite State Machines in HDL — dono assignment styles ko combine karta hai.
Number Systems and Bit-Widths — literals mein width/base kyun hoti hai.
Testbenches — jahan sequential initial/begin..end code software ki tarah sach mein chalta hai.