Synthesis to gate-level netlist: Exercises — Hardware deep dive

Intuition How to use this page

Work each problem before opening its Solution callout. The problems climb five levels: L1 Recognition (know the words), L2 Application (plug the formula), L3 Analysis (compare and diagnose), L4 Synthesis (design a fix / build a chain), L5 Mastery (put everything together on a full path). Two timing rules run through the page, both from the parent note, HDL & Digital Design Flow → Synthesis: $setup slack = T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c})$ $hold slack = t_{c q} + t_{l o g i c}^{min} - (t_{h} + t_{u n c})$ A positive slack means the timing is met; a negative slack is a violation the tool must fix. Setup asks "is the data fast enough to arrive before the next edge?"; hold asks "is the data slow enough not to race past the same edge?" We derive both formulas from scratch just below, so no equation is handed to you unearned.

Before we start, one reminder of what each symbol means, so no notation is unearned:

Definition The time-eaters (all measured in nanoseconds, ns)

$T$ — the clock period: the gap in time between two clock ticks. This is your setup budget.
$t_{c q}$ — clock-to-Q delay: after the launching flip-flop sees a tick, this is how long until its output actually changes. See Setup and Hold Time in Flip-Flops.
$t_{l o g i c}$ — the combinational logic delay: time for the signal to ripple through the gates between the two flops. This is the part synthesis controls. Its shortest possible value is $t_{l o g i c}^{min}$ (used for hold).
$t_{s u}$ — setup time: the data must be steady this long before the capturing tick, so it shifts the deadline earlier.
$t_{h}$ — hold time: the data must stay steady this long after the capturing tick, so new data must not arrive too soon.
$t_{u n c}$ — clock uncertainty: a safety margin for jitter/skew, from Clock Skew and Uncertainty.

Where the two formulas come from

Both slack rules are just "deadline minus arrival," read off one timeline. The figure below is that timeline: the launching flop ticks at time $0$ , the capturing flop ticks again one period later at time $T$ .

Figure — Synthesis to gate-level netlist

Intuition Deriving the setup slack step by step

Look at the top timeline in the figure. (1) WHAT: the launching flop ticks at $t = 0$ ; its output does not change until $t_{c q}$ later, so the data starts travelling at $t = t_{c q}$ . (2) WHY: a real flop cannot output instantly. (3) WHAT IT LOOKS LIKE: the blue segment. (4) The data then crawls through the gates for $t_{l o g i c}$ — the orange segment — arriving at the capturing flop's D pin at time $t_{c q} + t_{l o g i c}$ . (5) The capturing tick is at $t = T$ , but the data must be steady $t_{s u}$ before that, so the true deadline is $T - t_{s u}$ (pulled earlier — the green segment). (6) Add the safety margin $t_{u n c}$ , pulling the deadline to $T - t_{s u} - t_{u n c}$ . The condition "arrive before deadline" is: $t_{c q} + t_{l o g i c} \leq T - t_{s u} - t_{u n c}$ Move everything to one side and define the spare time as slack: $setup slack = T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c})$ That is exactly the parent note's inequality, now derived rather than declared.

Intuition Deriving the hold slack step by step

Now the bottom timeline. (1) WHAT: hold is about the same capturing tick at $t = 0$ (not the next one). The value the capturing flop grabbed on this edge must stay untouched for $t_{h}$ after the edge — that is the window $[0, t_{h}]$ (the green hold window). (2) WHY: if fresh data arrives inside that window, the flop may latch the new value instead of the one it was told to keep — a race. (3) WHAT IT LOOKS LIKE: the new data launched by the same edge appears at $t_{c q} + t_{l o g i c}^{min}$ — we use the shortest path because the earliest arriving data is the danger. (4) Safety: shift the window out by $t_{u n c}$ . Condition "new data arrives after the hold window closes": $t_{c q} + t_{l o g i c}^{min} \geq t_{h} + t_{u n c}$ Spare time = hold slack: $hold slack = t_{c q} + t_{l o g i c}^{min} - (t_{h} + t_{u n c})$ Notice $T$ never appears — that is why a slower clock cannot fix a hold violation.

Level 1 — Recognition

Recall Solution L1.1

Elaboration — read and parse the HDL, check syntax, build an internal model.
Translation to generic logic (GTECH) — turn behavior into a technology-independent Boolean network. GTECH ("generic technology") is the tool's built-in placeholder gate library: abstract AND/OR/MUX/flop symbols with no delay or area yet, used only to reason about the logic before real cells are chosen.
Technology mapping — cover that generic (GTECH) network with real cells from the .lib.
Optimization — resize, buffer, restructure to meet the constraints.

Mnemonic from the parent: "Every Genius Team Optimizes."

Recall Solution L1.2

(a) Netlist — an instantiated standard cell.
(b) RTL — a behavioral always block (this is what synthesis replaces).
(c) RTL — an assign with Boolean operators, not a cell instance.
(d) Netlist — an instantiated flip-flop cell.

The precise rule (not the oversimplified one): a gate-level netlist's combinational and sequential logic is expressed only as cell instances CELLNAME uN (...) — never as +, ?:, if, or always @(posedge) behavior. It absolutely still contains the ordinary structural scaffolding of any Verilog module: a module/endmodule header, input/output/inout port declarations, wire declarations for the internal nets that connect cells, and sometimes assign statements only for trivial pass-throughs (a net tied straight to a port or to a constant) or benign parameters/attributes the vendor emits. So "no +, no ?:, no always" is a rule about where the logic lives (in cells), not a claim that the file is nothing but instance lines.

Recall Solution L1.3

(i) clock period → SDC (constraints).
(ii) menu of gates + delays → .lib (technology library, see Standard Cell Libraries and .lib Timing Models).
(iii) desired behavior → RTL source.

Level 2 — Application

Recall Solution L2.1

Sum everything the data experiences, subtract from the budget $T$ : $slack = 3 - (0.25 + 2.1 + 0.2 + 0.1) = 3 - 2.65 = + 0.35 ns$ Positive slack → timing met, no fix needed. (This path sits in the green top-left quadrant of the figure.)

Recall Solution L2.2

Set slack to exactly zero and solve for $t_{l o g i c}$ : $0 = T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c}) ⟹ t_{l o g i c} = T - t_{c q} - t_{s u} - t_{u n c}$ $t_{l o g i c} = 2.5 - 0.3 - 0.18 - 0.12 = 1.9 ns$ Any logic at or below 1.9 ns passes; above it, violation.

Recall Solution L2.3

Use the hold formula (no $T$ inside it, so the missing $T$ is fine): $hold slack = t_{c q} + t_{l o g i c}^{min} - (t_{h} + t_{u n c}) = 0.25 + 0.12 - (0.2 + 0.05) = 0.37 - 0.25 = + 0.12 ns$ Positive → hold met. The new data (arriving at $0.37$ ns) comes after the hold window closes ( $0.25$ ns), so no race. The absence of $T$ is not a problem — hold never uses it.

Recall Solution L2.4

A conditional select of two inputs is a 2:1 multiplexer:

MUX2X1 u1 (.A(q), .B(p), .S(sel), .Y(y));

The ?: disappears; the structural instance is the netlist form. (Which input is A vs B depends on the cell's polarity, but the cell is a MUX2X1.)

Level 3 — Analysis

Recall Solution L3.1

(a) $slack = 2 - (0.2 + 2.0 + 0.15 + 0.1) = 2 - 2.45 = - 0.45 ns (violation)$ (b) To reach zero slack we must recover the whole $0.45$ ns from the logic. The new logic delay must be: $t_{l o g i c}^{n e w} = 2.0 - 0.45 = 1.55 ns$ So the tool needs a logic structure at 1.55 ns or faster (e.g. carry-lookahead instead of ripple). This path was in the orange (setup-fail) quadrant; the fix moves it back to green.

Recall Solution L3.2

(a) Helps — bigger gates switch faster ( $t_{l o g i c} ↓$ ); cost: more area, more power, and larger load on the previous stage.
(b) Helps — carry-lookahead shortens the critical path; cost: more area/power (more gates).
(c) Helps — lowering frequency raises $T$ , so the budget grows; cost: the chip runs slower overall (may violate the spec).
(d) Hurts — more logic levels increase $t_{l o g i c}$ ; this makes the violation worse.

Recall Solution L3.3

(a) $hold slack = 0.15 + 0.03 - (0.25 + 0.05) = 0.18 - 0.30 = - 0.12 ns (violation)$ (b) No. $T$ does not appear in the hold formula, so doubling it changes hold slack by exactly zero. This is the bottom-left (blue) quadrant trap. (c) The real fix is to slow the shortest path: insert delay buffers so $t_{l o g i c}^{min}$ rises. We need hold slack $\geq 0$ , i.e. raise $t_{l o g i c}^{min}$ by at least $0.12$ ns (from $0.03$ to $\geq 0.15$ ns). Then $hold slack = 0.15 + 0.15 - 0.30 = 0.00$ ns, just met.

Recall Solution L3.4

The capturing flop needs the data steady $t_{s u}$ before its tick at $T$ , and we reserve a further $t_{u n c}$ for clock jitter/skew, so the effective deadline is pulled earlier to $T - t_{s u} - t_{u n c}$ ; the leftover gap between the end of the orange $t_{l o g i c}$ segment and that deadline is the green slack segment. See Static Timing Analysis (STA) for how tools report exactly this gap.

Level 4 — Synthesis (build a fix)

Recall Solution L4.1

(a) $slack = 2.5 - (0.3 + 2.1 + 0.2 + 0.15) = 2.5 - 2.75 = - 0.25 ns (fail)$ (b) Ripple still fails (it's the current value). Choose carry-lookahead ( $t_{l o g i c} = 1.6$ ): $slack = 2.5 - (0.3 + 1.6 + 0.2 + 0.15) = 2.5 - 2.25 = + 0.25 ns ✓$ (c) Slack is $+ 0.25$ ns — timing met. Cost: $+ 40%$ adder area (the timing↔area trade-off).

Worked example L4.2 — Build the two-flop path map

You are given the RTL, where a and b come from two source registers clocked by clk:

always @(posedge clk) q <= a & b;

Sketch (in words + cell instances) the full netlist shape of one input register, the combinational AND, and the capturing register, naming every net so the whole two-flop timing path is visible.

Recall Solution L4.2

The launching flip-flop drives net a from its Q; the AND cell produces net w; the capturing flip-flop stores w. A real netlist also declares those internal nets as wires:

wire a, b, w;                            // internal nets are declared
DFFX1  u0 (.D(a_in), .CK(clk), .Q(a));   // launching FF: source of net a
AND2X1 u1 (.A(a),    .B(b),    .Y(w));   // combinational logic
DFFX1  u2 (.D(w),    .CK(clk), .Q(q));   // capturing FF: stores the result

The timing path runs, all inside one $T$ : u0.CK tick → u0.Q=a ( $t_{c q}$ ) → AND2X1 u1 ( $t_{l o g i c}$ ) → u2.D=w must be steady $t_{s u}$ before u2's next tick. Naming the nets (a, w) makes the launch point (u0.Q) and capture point (u2.D) explicit — that is exactly the span the setup and hold constraints measure. See RTL Design and the Synthesizable Subset.

Recall Solution L4.3

(a) Setup: $2 - (0.2 + 1.2 + 0.15 + 0.1) = 2 - 1.65 = + 0.35 ns ✓$ Hold: $0.2 + 0.05 - (0.3 + 0.1) = 0.25 - 0.40 = - 0.15 ns (fail)$ Only hold fails — this is the bottom-left (blue) quadrant. (b) After the buffer, $t_{l o g i c}^{min} = 0.45$ : hold $= 0.2 + 0.45 - (0.3 + 0.1) = 0.65 - 0.40 = + 0.25 ns ✓$ Setup is unchanged ( $+ 0.35$ ns) because we only touched the short path, not the critical long path. (c) Setup is limited by the longest path; adding delay there would eat setup slack and could cause a new setup violation. The shortest path is what hold cares about, and it has plenty of setup room to spare — so buffering it fixes hold "for free" on setup.

Recall Solution L4.4

At $T = 4$ , the sum of the four terms is $4 - 0.4 = 3.6$ ns. The minimum period is when slack $= 0$ , i.e. $T_{min}$ equals that sum: $T_{min} = 3.6 ns ⟹ f_{ma x} = \frac{1}{3.6 ns} \approx 0.2778 GHz = 277.8 MHz$ So you can push the clock up until $T = 3.6$ ns before the setup path breaks. (Hold is unaffected — it does not depend on $T$ .)

Level 5 — Mastery

Recall Solution L5.1

(a) $slack = 2 - (0.2 + 1.75 + 0.15 + 0.15) = 2 - 2.25 = - 0.25 ns (fail)$ (b) With CLA logic $= 1.35$ : $slack = 2 - (0.2 + 1.35 + 0.15 + 0.15) = 2 - 1.85 = + 0.15 ns ✓$ (c) Now $t_{c q} = 0.28$ : $slack = 2 - (0.28 + 1.35 + 0.15 + 0.15) = 2 - 1.93 = + 0.07 ns ✓$ Still positive — the design meets timing, but the margin shrank from $0.15$ ns to $0.07$ ns because the CLA's larger input capacitance loaded the driving flop and stretched its $t_{c q}$ from $0.20$ to $0.28$ ns. That $0.08$ ns of extra clock-to-Q delay ate more than half the freshly-won slack — a concrete instance of the L3 lesson that a local speed-up can charge you back elsewhere on the path. The path still closes, but the shrunken margin warns the optimizer it may need to also upsize the driving flop or split the load if any further change nibbles at that $0.07$ ns. (d) The logic swap happens in Stage 4 — Optimization (after tech mapping). Deciding where the cells physically sit is Place and Route, a separate physical-design step — see Place and Route (Physical Design).

Recall Solution L5.2

Require slack $\geq 0.1$ : $T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c}) \geq 0.1$ $T \geq 0.1 + (0.25 + 1.2 + 0.2 + 0.1) = 0.1 + 1.75 = 1.85 ns$ The SDC must set $T \geq 1.85 ns$ (so $f \leq 540.5$ MHz). Choosing exactly $T = 1.85$ ns gives slack $= + 0.1$ ns.

Recall Solution L5.3

(a) $hold slack = 0.2 + 0.05 - (0.2 + 0.1) = 0.25 - 0.30 = - 0.05 ns$ (b) Negative → hold violation. The new data reaches u2.D too soon, corrupting the value u2 was still holding from the previous edge. (Bottom-left blue quadrant.) (c) No. Hold slack has no $T$ in it — a slower clock does not help; a hold violation is stubborn. (d) The tool slows the shortest path by inserting delay buffers (or larger-delay cells) to raise $t_{l o g i c}^{min}$ . It must add at least $0.05$ ns (bringing $t_{l o g i c}^{min}$ from $0.05$ to $\geq 0.10$ ns), after which hold slack $= 0.2 + 0.10 - 0.30 = 0.00$ ns, just met. See Setup and Hold Time in Flip-Flops.

Recall Solution L5.4

(a) Setup: $1.5 - (0.2 + 1.3 + 0.1 + 0.05) = 1.5 - 1.65 = - 0.15 ns (fail)$ Hold: $0.2 + 0.04 - (0.25 + 0.05) = 0.24 - 0.30 = - 0.06 ns (fail)$ (b) Both fail → the bottom-right (red) quadrant. (c) Two independent fixes: (setup) speed up the long path (faster logic / bigger $T$ ) to recover $0.15$ ns; (hold) slow the short path with $\geq 0.06$ ns of buffer delay. Neither fix helps the other — they touch different paths and different formulas.

Worked example L5.5 — Spot the non-synthesizable trap

This RTL simulates perfectly but the tool errors during synthesis. Which lines are the culprits and why?

initial y = 0;
always @(*) begin
  #5 y = a & b;
end

Recall Solution L5.5

initial y = 0; — an initial block used to set logic has no hardware meaning (there is no "time zero" for a gate); synthesis ignores or rejects it.
#5 — a delay describes simulation timing, not a physical gate; it is non-synthesizable.

Both simulate fine but are outside the synthesizable subset. Fix: drop #delays and use registers/reset for initialization. This is the parent's mistake "if it simulates, it synthesizes" — it does not. See RTL Design and the Synthesizable Subset.

Recall One-line self-test

Setup constraint ::: $t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c} \leq T$ , equivalently setup slack $= T - (t_{c q} + t_{l o g i c} + t_{s u} + t_{u n c}) \geq 0$ . Where does the setup deadline $T - t_{s u} - t_{u n c}$ come from ::: the data must be steady $t_{s u}$ before the next tick at $T$ , minus a further $t_{u n c}$ for jitter/skew. Hold constraint ::: $t_{c q} + t_{l o g i c}^{min} \geq t_{h} + t_{u n c}$ , equivalently hold slack $= t_{c q} + t_{l o g i c}^{min} - (t_{h} + t_{u n c}) \geq 0$ . Why is there no $T$ in the hold formula ::: hold compares two events relative to the same clock edge, so the next period never enters. Which term does synthesis control for setup ::: $t_{l o g i c}$ — by choosing/sizing/restructuring the gates to make it smaller. How does the tool fix a hold violation ::: It adds delay (buffers) on the shortest path to raise $t_{l o g i c}^{min}$ ; a slower clock does not help hold. Which step places cells physically ::: Place and Route, not synthesis.