Synthesis to gate-level netlist

3.5.7 · Hardware › HDL & Digital Design Flow

Synthesis KYA hai?

Teen inputs hamesha zaroori hote hain:

1. RTL source — tumhara always/process behavioral code.
2. Technology library (.lib) — available gates ka menu, jisme har ek ki delay, area, power hoti hai.
3. Constraints (SDC) — clock period, input/output delays, area budget, wagera.

Output ek netlist hoti hai: syntactically abhi bhi Verilog hai, lekin ab isme koi +, if, ya always @(posedge) behavior nahi hai — sirf instantiated cells hain jaise AND2X1 u5 (.A(...), .B(...), .Y(...));.

HOW it works — chaar stages

RTL ──► [1 Elaboration] ──► [2 Translation to      ──► [3 Technology  ──► [4 Optimization] ──► Netlist
         + parse/check       generic Boolean/RTL         mapping to
                             (GTECH) logic]              real .lib cells]

Stage 1 — Elaboration/Parsing. HDL padho, syntax check karo, parameters resolve karo, hierarchy banao. Kyun: jab tak tool ka ek internal model nahi hoga, kuch bhi nahi ho sakta.

Stage 2 — Translation to generic logic (GTECH). Behavior → technology-independent Boolean network. assign y = a & b | c; ek abstract AND/OR graph ban jaata hai. Kyun: kisi specific vendor ke gates commit karne se pehle Boolean logic optimize karo.

Stage 3 — Technology mapping. Boolean network ko actual library cells se cover karo (jaise generic 3-input logic ko ek AOI21X1 se replace karo agar woh exist karta ho). Kyun: sirf real cells ki real delay/area hoti hai, isliye humein unhe choose karna padega taaki pata chale ki timing meet ho rahi hai ya nahi.

Stage 4 — Optimization. Logic restructure karo, cells resize/buffer karo, SDC constraints satisfy karne ke liye paths balance karo. Kyun: pehli legal mapping rarely sabse fast ya sabse choti hoti hai.

Core numbers: timing closure

Synthesis mostly timing hit karne ke liye hoti hai. Key inequality ko scratch se derive karo.

Setup: signal FF1 se ek clock edge pe launch hota hai, aur agali edge pe, ek clock period $T$ baad, FF2 se capture hona chahiye.

Data travel karne ke liye available time = ek clock period. Lekin do cheezein ise khaati hain:

• Launching flop instantly output nahi karta: clock-to-Q delay $t_{cq}$.
• Capturing flop ko data chahiye ki woh apni edge se pehle stable ho: setup time $t_{su}$.

Toh combinational logic ke liye bacha hua time (plus ek margin/uncertainty) hai:

$T-t_{cq}-t_{su}-t_{unc}$

Actual logic delay ko fit karna zaroori hai:

Har term kyun: $t_{cq}$ start mein delay karta hai, $t_{logic}$ woh hai jo synthesis control karta hai (gates choose karke), $t_{su}$ deadline ko pehle shift karta hai, $t_{unc}$ clock jitter/skew estimate cover karta hai. Sab kuch ek period $T$ ke andar fit hona chahiye.

Negative slack pe synthesis ki reaction: gates upsize karo (faster lekin bade/zyada power wale), buffers add karo, logic restructure karo (jaise AND-tree balance karo), ya arithmetic restructure karo (carry-lookahead vs ripple). Yahi area–power–timing trade-off hai.

Worked examples

Common mistakes

80/20 — The vital few

Flashcards

Connections

• RTL Design and the Synthesizable Subset
• Static Timing Analysis (STA)
• Standard Cell Libraries and .lib Timing Models
• Place and Route (Physical Design)
• Setup and Hold Time in Flip-Flops
• Clock Skew and Uncertainty
• HDL & Digital Design Flow

Concept Map