Worked examples — Timing analysis basics (static timing)

Two formulas power everything (both from the parent). We restate them once so no symbol is unearned:

A reminder of what each letter is, in plain words:

---

The scenario matrix

Every timing question you can be asked is one cell of this grid. The last column names the example that covers it.

#	Case class	What is stressed	Covered by
A	Setup, comfortable	slack $>0$	Ex 1
B	Setup, exactly on the edge	slack $=0$ (limiting value)	Ex 2
C	Setup, violation	slack $<0$	Ex 3
D	Hold, pass	fast path still slow enough	Ex 4
E	Hold, violation	fast path too fast	Ex 5
F	Degenerate: zero combinational logic ($t_{comb}=0$)	flop-to-flop, worst hold case	Ex 5
G	Positive skew	helps setup, hurts hold	Ex 6
H	Negative skew	hurts setup, helps hold	Ex 7
I	Real-world word problem	pick the right frequency	Ex 8
J	Exam twist: find max allowed logic delay	solve inequality for $t_{comb}$	Ex 9

We now walk all ten cells.

---

Setup axis: comfortable → edge → violation

The figure above is one timeline. The launch edge is at $0$, the capture edge at $T_{clk}$. Data leaves at $t_{cq}$ (blue), arrives at $t_{cq}+t_{comb}$ (orange dot), and the deadline (dashed red) sits at $T_{clk}-t_{su}$. Slack is the green gap; if orange sits past the red line, slack goes negative.

---

Hold axis: pass → violation → zero-logic degenerate

Hold is a same-edge race. Both flops feel the tick at $0$. The old value inside FF2 must survive until $t_h$ (red line). The new value racing through the fastest path arrives at $t_{cq}+t_{comb,min}$ (orange). If orange lands left of the red line, the new value overwrites the old too early — a hold violation.

---

Skew axis: positive vs negative

Skew slides the capture clock edge. Positive skew (capture later, orange edge moves right) hands setup more time but makes the hold "hold-until" line move right too, so hold gets harder. Negative skew does the reverse. The figure shows both slides on one axis.

---

Word problem and exam twist

---

Recall

Recall Which extreme path does each check use, and why?

Setup → longest path (fear arriving late). Hold → shortest path (fear arriving too early).

Recall Ex 5's fix for a zero-logic hold violation?

Insert buffer delay in the data path (raise $t_{comb,min}$). Slowing the clock cannot help — $T_{clk}$ isn't in the hold equation.

Recall Positive skew: effect on setup and hold?

Helps setup (later deadline), hurts hold (later "hold-until" bar). Ex 6 shows both.

Connections

• Timing analysis basics (static timing) — the parent that derives the two constraints.
• Setup and hold time
• Critical path and pipelining
• Clock skew and clock trees
• Metastability
• Flip-flops and sequential logic
• HDL & Digital Design Flow