Timing analysis basics (static timing): Exercises — Hardware deep dive

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Work each problem on paper first, then open the collapsible solution. The problems climb a ladder: from recognizing which formula applies, up to synthesizing a fix and mastering the trade-offs. Everything you need lives in the parent note Timing analysis basics (static timing). Below, the two core constraints are the boxed setup/hold inequalities from the parent note; the two slack lines are just those same inequalities rearranged into a "pass margin" (required time − arrival time). Keep all four in view:

Core constraints (from the parent note):

Setup: $t_{c q} + t_{co mb, ma x} + t_{s u} \leq T_{c l k} + t_{s k e w}$
Hold: $t_{c q} + t_{co mb, min} \geq t_{h} + t_{s k e w}$

Derived slack forms (constraint rearranged as margin):

Setup slack $= (T_{c l k} + t_{s k e w}) - (t_{c q} + t_{co mb, ma x} + t_{s u})$
Hold slack $= (t_{c q} + t_{co mb, min}) - (t_{h} + t_{s k e w})$

A constraint holds iff its slack is $\geq 0$ — so the two slack lines carry no new physics, they just report the two core constraints as a single signed number each.

Here $t_{c q}$ is the flip-flop's clock-to-Q delay (how long after the clock edge the output changes), $t_{co mb}$ is the combinational logic delay along a path, $t_{s u}$ / $t_{h}$ are setup / hold times, $T_{c l k}$ is the clock period, and $t_{s k e w} = t_{c a pt u r e} - t_{l a u n c h}$ is the clock skew (how much later the capturing flop's clock arrives than the launching flop's — it can be negative if the capture clock arrives earlier).

Definition What

$t_{co mb, ma x}$ and $t_{co mb, min}$ actually mean These are not two numbers on one wire. Between the same launch and capture flops there can be many combinational routes (different gate chains).

$t_{co mb, ma x}$ = the propagation (worst / longest) delay — the slowest route data can take. Used for setup (fear of arriving too late).
$t_{co mb, min}$ = the contamination (best / shortest) delay — the fastest route, the earliest a changing output can begin to disturb FF2. Standard-cell libraries publish this as the contamination delay spec. Used for hold (fear of arriving too early). "Contamination" = the moment the output first stops being the old value; "propagation" = the moment it has fully settled to the new value. Hold cares about the first flicker (min), setup about the final settle (max).

The one picture we keep returning to — a signal launched by FF1, running through logic, and needing to be settled at FF2 before its next edge:

Figure — Timing analysis basics (static timing)

Level 1 — Recognition

Goal: pick the right formula and the right path (max vs min).

Recall Solution L1.1

Setup → longest path. Setup fears data arriving too late; the slowest route (the propagation delay, $t_{co mb, ma x}$ ) is the latest arrival. Hold → shortest path. Hold fears data arriving too early and corrupting the capture at the same edge; the fastest route (the contamination delay, $t_{co mb, min}$ ) is the earliest disturbance.

Recall Solution L1.2

Setup constraint at equality: $T_{c l k, min} = t_{c q} + t_{co mb, ma x} + t_{s u} = 0.25 + 3.0 + 0.4 = 3.65 ns$ .

Recall Solution L1.3

False. The hold equation $t_{c q} + t_{co mb, min} \geq t_{h} + t_{s k e w}$ contains no $T_{c l k}$ . Hold is a same-edge race; the clock period is irrelevant to it.

Level 2 — Application

Goal: plug numbers into setup, hold, slack, and $f_{ma x}$ .

Recall Solution L2.1

$T_{c l k, min} = 0.2 + 6.3 + 0.5 = 7.0$ ns. $f_{ma x} = \frac{1}{7.0 ns} = \frac{1}{7 \times 1 0 ^{- 9} s} \approx 142.9 MHz$

Recall Solution L2.2

Arrival (required by data) $= t_{c q} + t_{co mb, ma x} + t_{s u} = 7.0$ ns. Setup slack $= T_{c l k} - 7.0 = 6.5 - 7.0 = - 0.5 ns$ → fails by 0.5 ns. The deadline (6.5 ns) arrives before the data can settle (7.0 ns).

Recall Solution L2.3

Earliest arrival $= t_{c q} + t_{co mb, min} = 0.2 + 0.15 = 0.35$ ns. Hold slack $= 0.35 - t_{h} = 0.35 - 0.5 = - 0.15 ns$ → hold violation. New data races to FF2 in 0.35 ns but must stay away until 0.5 ns after the edge.

Level 3 — Analysis

Goal: reason about skew (both signs), and about which path each violation lives on.

Recall Solution L3.1

Start from the formula and substitute term by term: $Setup slack = (T_{c l k} + t_{s k e w}) - (t_{c q} + t_{co mb, ma x} + t_{s u})$ At $t_{s k e w} = 0$ the slack was $0.3$ , so $T_{c l k} - (t_{c q} + t_{co mb, ma x} + t_{s u}) = 0.3$ . Adding skew only touches the $+ t_{s k e w}$ term: $new slack = old 0.3 + + 0.4 t_{s k e w} = + 0.7 ns$ Positive skew helps setup — because it enters with a $+$ sign, a later capture edge pushes the deadline back, giving data more time.

Recall Solution L3.2

Substitute into the hold-slack formula term by term: $Hold slack = (t_{c q} + t_{co mb, min}) - (t_{h} + t_{s k e w})$ Here $t_{s k e w}$ appears inside a subtraction, so it enters slack with a $-$ sign. At $t_{s k e w} = 0$ the slack was $0.1$ ; adding $+ 0.4$ of skew subtracts $0.4$ : $new slack = old 0.1 - 0.4 t_{s k e w} = - 0.3 ns$ → now a hold violation. Positive skew hurts hold: delaying the capture edge means the old value must be held longer, so early-arriving new data corrupts it. Same $t_{s k e w}$ , opposite signs in the two formulas — that is the whole asymmetry. See the arrows below.

Recall Solution L3.3

Negative skew flips both signs relative to L3.1–L3.2. Substitute $t_{s k e w} = - 0.3$ : $Setup slack = 0.5 + t_{s k e w} = 0.5 + (- 0.3) = + 0.2 ns$ $Hold slack = 0.4 - t_{s k e w} = 0.4 - (- 0.3) = + 0.7 ns$ Negative skew hurts setup (deadline pulled earlier, less time — slack shrank) and helps hold (the old value need be held for less time — slack grew). This is the exact mirror of positive skew. Both paths still pass here, but you can see the trade run in the opposite direction.

Recall Solution L3.4

Slowing the clock only relaxes setup (it enlarges $T_{c l k}$ ). Since the failure vanished, it was a setup violation, living on the longest / critical path ( $t_{co mb, ma x}$ ). A hold failure would have been unaffected.

Level 4 — Synthesis

Goal: choose and size a fix, not just detect a problem.

Recall Solution L4.1

Current hold slack $= (0.2 + 0.1) - 0.5 = - 0.2$ ns. We need to add at least $0.2$ ns of delay. Buffers needed $= ⌈ 0.2/0.05 ⌉ = ⌈ 4 ⌉ = 4$ buffers (adding exactly $0.20$ ns → new slack $= 0.0$ ns, which passes at $\geq 0$ ). Note we add delay to the data path, never slow the clock — hold is $T_{c l k}$ -independent.

Recall Solution L4.2

Setup slack $= T_{c l k} - (t_{c q} + t_{co mb, ma x} + t_{s u}) = 6.0 - (0.2 + 5.0 + 0.4) = 6.0 - 5.6 = + 0.4 ns$ → still passes. Because the buffers sit on the short path only, the critical (long) path is untouched, so the setup fix is not disturbed.

Recall Solution L4.3

Arrival $= 0.3 + 4.2 + 0.5 = 5.0$ ns. We need $5.0 \leq 0.9 T_{c l k}$ , i.e. $T_{c l k} \geq 5.0/0.9 \approx 5.556 ns$ (so $f \leq 180$ MHz gives $\geq 10%$ margin).

Level 5 — Mastery

Goal: integrate everything, including the physical why, edge cases, and the timing exceptions (multi-cycle and false paths).

Recall Solution L5.1

(a) Setup: $T_{c l k, min} = t_{c q} + 0 + t_{s u} = 0.2 + 0.3 = 0.5 ns$ . Even with no logic, the register overhead sets a floor on the period. (b) Hold: $t_{c q} + t_{co mb, min} = 0.2 + 0 = 0.2$ ns; require $\geq t_{h} = 0.4$ ns → $0.2 < 0.4$ → hold FAILS by 0.2 ns. Back-to-back flops are the classic hold-violation shape: the new value shoots through in just $t_{c q}$ , faster than the old value can be captured. Real libraries guarantee $t_{c q} \geq t_{h}$ or insert delay to prevent exactly this — this is why metastability and hold are cousins.

Recall Solution L5.2

(a) Setup slack $= (T_{c l k} + t_{s k e w}) - arrival = (5.0 + t_{s k e w}) - 5.2 = t_{s k e w} - 0.2$ . Set $\geq 0$ : $t_{s k e w} - 0.2 \geq 0 \Rightarrow t_{s k e w} \geq 0.2 ns$ So the minimum positive skew that rescues setup is $t_{s k e w} = 0.2$ ns (setup slack becomes exactly $0$ ). (b) With $t_{s k e w} = + 0.2$ ns, hold slack drops by that same amount (it enters hold with a $-$ sign): $new hold slack = 0.5 - t_{s k e w} = 0.5 - 0.2 = + 0.3 ns \to still passes.$ Here we bought the setup fix with skew and the hold path had enough cushion (0.5 ns) to absorb the 0.2 ns cost. This is useful skew — a real optimization, but only safe when hold margin can afford it. Had the hold slack started below $0.2$ ns, this same skew would have created a hold violation.

Recall Solution L5.3

Setup slack $= (T_{c l k} + t_{s k e w}) - (t_{c q} + t_{co mb, ma x} + t_{s u}) = (5.0 + 0.1) - (0.25 + 3.9 + 0.35) = 5.1 - 4.5 = + 0.6 ns$ ✅ Hold slack $= (t_{c q} + t_{co mb, min}) - (t_{h} + t_{s k e w}) = (0.25 + 0.3) - (0.2 + 0.1) = 0.55 - 0.3 = + 0.25 ns$ ✅ Both positive → the path signs off. This is what a passing STA report row looks like.

Recall Solution L5.4

(a) With $t_{co mb} = 0.3$ : Setup slack $= T_{c l k} - (t_{c q} + t_{co mb} + t_{s u}) = 1.0 - (0.2 + 0.3 + 0.4) = 1.0 - 0.9 = + 0.1$ ns ✅ (barely). Hold slack $= (t_{c q} + t_{co mb}) - t_{h} = (0.2 + 0.3) - 0.6 = 0.5 - 0.6 = - 0.1$ ns ❌. (b) Add $Δ$ to the route. Since it is the same wire for both checks, $t_{co mb}$ becomes $0.3 + Δ$ in both formulas: $Hold slack = (0.5 + Δ) - 0.6 = Δ - 0.1 \geq 0 \Rightarrow Δ \geq 0.1$ $Setup slack = 1.0 - (0.9 + Δ) = 0.1 - Δ \geq 0 \Rightarrow Δ \leq 0.1$ The only value satisfying both is $Δ = 0.1$ ns exactly — a razor edge with zero margin on either side. Any real-world variation (a slightly faster or slower buffer, temperature drift) tips one check negative. Buffering trades hold slack for setup slack on the same wire, so on a single shared route it can never create margin for both at once. The real fix: restructure the logic so the fast and slow concerns live on different physical routes, or pipeline to shorten the long path, or retime the flops. See Critical path and pipelining.

Definition Timing exceptions — multi-cycle and false paths

STA's default rule is "data launched at one edge must be captured at the very next edge." Two exceptions override that default:

Multi-cycle path (MCP): a path the designer tells the tool is allowed $N$ clock cycles instead of 1 (e.g. a slow arithmetic unit whose result is only read every 3rd cycle). The setup deadline is stretched: $t_{c q} + t_{co mb, ma x} + t_{s u} \leq N \cdot T_{c l k} + t_{s k e w}$ . Hold is usually still checked against a nearby edge (default edge $- 1$ from the capture), not relaxed by $N$ — a common source of MCP hold bugs.
False path: a structural path that can never carry a real transition (e.g. mutually exclusive select lines that can't both be active). The designer marks it false so the tool ignores it entirely — otherwise a physically impossible path could masquerade as the critical path and needlessly lower $f_{ma x}$ . Both are constraints the engineer asserts, not facts the tool derives — assert them wrongly and STA will "pass" a chip that actually fails silicon.

Recall Solution L5.5

Arrival (data required time) $= t_{c q} + t_{co mb, ma x} + t_{s u} = 0.3 + 8.0 + 0.4 = 8.7$ ns. (a) Single-cycle setup slack $= T_{c l k} - 8.7 = 3.0 - 8.7 = - 5.7 ns$ → fails badly. (b) With a 3-cycle exception the deadline is $3 \cdot T_{c l k} = 9.0$ ns: setup slack $= 9.0 - 8.7 = + 0.3 ns$ → passes. The path was never actually broken; the default one-cycle assumption was wrong for it. (c) No. Hold is still evaluated at a near edge (by default one cycle from launch), so the MCP does not loosen hold — you must still satisfy $t_{c q} + t_{co mb, min} \geq t_{h}$ . Forgetting this is the classic MCP hold trap.

Recall Solution L5.6

Once the false path is excluded, the true critical path sets the period: $T_{c l k, min} = 6.0$ ns. $f_{ma x} = \frac{1}{6.0 ns} \approx 166.7 MHz$ The chip was always capable of ~167 MHz; the false path was a phantom limit. Caveat: marking a path false is a promise that it truly cannot toggle — if that promise is wrong, silicon fails while STA reports "clean."

Recall

Recall Minimum

$T_{c l k}$ when there is zero combinational logic $t_{c q} + t_{s u}$ — the register overhead alone sets a floor; logic delay only adds to it.

Recall How do you fix a hold violation, and how many buffers?

Add delay to the short data path (never slow the clock). Number of buffers $= ⌈(hold deficit) / (delay per buffer)⌉$ .

Recall What must both be true for a path to sign off?

Setup slack $\geq 0$ and hold slack $\geq 0$ — two separate checks on two path extremes.

Recall What does negative skew (capture clock early) do?

Opposite of positive skew: it hurts setup (deadline pulled earlier) and helps hold (old value held for less time).

Recall What is a multi-cycle path, and does it relax hold?

A path the designer allows $N$ cycles instead of 1, so setup deadline becomes $N \cdot T_{c l k}$ . It does not relax hold — hold is still checked at the default near edge.

Recall What is a false path?

A structurally-present route that can never carry a real transition; the designer marks it so STA ignores it, preventing a phantom path from limiting $f_{ma x}$ .

Recall Difference between

$t_{co mb, min}$ and $t_{co mb, ma x}$ ? $t_{co mb, min}$ = contamination (fastest) delay, used for hold; $t_{co mb, ma x}$ = propagation (slowest) delay, used for setup.

Exercises — Timing analysis basics (static timing)