Foundations — Timing analysis basics (static timing)

This page assumes you have seen none of the notation in the parent note. We build every letter, every subscript, and every picture before it is ever used. If a smart 12-year-old can read a clock and a ruler, they can read this.

0 — The one machine you must picture first

Everything in timing analysis happens inside a tiny fixed structure. Draw it once, keep it in your head forever:

Two little boxes that remember a bit (flip-flops), a cloud of gates between them (combinational logic), and a single wire (the clock) that ticks both boxes at the same time. That's it. Timing analysis is the study of this one picture.

We will meet these again in Flip-flops and sequential logic. For now: launch box → cloud → capture box, all sharing one clock.

1 — The clock, and $T_{clk}$

Why the topic needs it. Every deadline in timing analysis is measured against $T_{clk}$: data must arrive within one period. It is the total time budget per cycle.

Why $\frac{1}{T}$ and not something else? Because "events per second" is literally the reciprocal of "seconds per event." Period and frequency are two names for the same beat, flipped over. This is why Critical path and pipelining cares about the slowest path — it directly caps $f$.

2 — Delays: $t_{cq}$ and $t_{comb}$

Nothing in electronics is instant. A wire and a transistor take time to respond. We give each source of delay its own name.

The subscript reads "clock-to-Q": from the clock edge to the Q output.

Why two of them, min and max? Different routes through the gate cloud have different lengths. We will need:

• $t_{comb,max}$ — the slowest possible route (the critical path).
• $t_{comb,min}$ — the fastest possible route (the short-cut).

Hold this thought: setup will fear the slow route, hold will fear the fast route. Same cloud, two extremes.

3 — The flip-flop's own rules: $t_{su}$ and $t_h$

A flip-flop is fussy about when you feed it data. It has two demands, and both are about a window around the tick.

Together these carve out a small forbidden window straddling the tick: no data changes allowed from $t_{su}$ before until $t_h$ after. Both are covered in depth in Setup and hold time.

4 — Two clocks that aren't quite together: $t_{skew}$

We said both flip-flops share one clock. In reality the clock wire is long, and the tick reaches FF2 slightly later (or earlier) than it reaches FF1. That difference has a name.

Picture: two drummers meant to beat in unison, but one hears the beat a hair later. The full story of why this happens and how it's controlled lives in Clock skew and clock trees.

Why the topic needs it. Skew shifts the capture deadline. A later capture tick gives the slow data more time (helps setup) but tightens the "don't arrive too early" rule (hurts hold). Every constraint gets a $\pm t_{skew}$ correction.

5 — Putting the timeline together

Now watch every symbol act on a single timeline. This is the whole derivation in one picture — read it left to right.

• At time $0$: the launch tick.
• After $t_{cq}$: FF1's output changes (data leaves).
• After a further $t_{comb}$: data arrives at FF2's input, at total time $t_{cq}+t_{comb}$.
• At time $T_{clk}$: the capture tick.
• The forbidden setup zone opens at $T_{clk}-t_{su}$.

The whole game: arrival ($t_{cq}+t_{comb}$) must land at or before the setup deadline ($T_{clk}-t_{su}$). That single race is the setup constraint the parent note derives. Every symbol you just learned is a landmark on this one timeline.

Prerequisite map

Read it top-down: the flip-flop and the clock are the roots; every delay and margin grows from them; all feed into STA at the bottom.

Equipment checklist

Cover the right side and test yourself. If any answer is fuzzy, reread its section above before the parent note.