Visual walkthrough — Timing analysis basics (static timing)

Step 0 — The two characters and the clock

We have two flip-flops in a row:

• FF1 = the launcher. It puts a fresh value onto the wire.
• FF2 = the catcher. It must snapshot that value cleanly.
• Between them sits combinational logic (gates: AND, OR, ...). It has no memory; it just delays and transforms. Its travel time we call $t_{comb}$.

Step 1 — When does the new data leave FF1?

WHAT. At the launch rising edge (call its time $0$), FF1 does not update its output instantly. There is a small internal delay — the clock-to-Q delay, written $t_{cq}$ — before Q actually changes.

WHY this quantity. Real transistors take time to switch. If we pretended $t_{cq}=0$ we would under-count the total travel time and wrongly declare the circuit fast enough. Honesty about $t_{cq}$ is the first brick.

PICTURE. The output Q of FF1 is flat until $t_{cq}$ after the edge, then it steps to the new value.

$t_{\text{launch\_data}}=\underset{\begin{array}{c}\text{time for FF1’s output}\\ \text{to react to the edge}\end{array}}{\underbrace{t_{cq}}}$

Step 2 — When does the data arrive at FF2's door?

WHAT. After leaving FF1, the signal walks through the gates. That walk takes $t_{comb}$. So arrival time at FF2's input D is the launch time plus the walk.

WHY. The signal is physically real; it cannot teleport across the logic. Adding $t_{comb}$ is just "start time + travel time = finish time."

PICTURE. The red data waveform at FF2's input rises one gap later than at FF1's output — that gap is $t_{comb}$.

$t_{\text{arrive}}=\underset{\text{leave FF1}}{\underbrace{t_{cq}}}+\underset{\begin{array}{c}\text{walk through}\\ \text{the gates}\end{array}}{\underbrace{t_{comb}}}$

Step 3 — The deadline: setup time before the next edge

WHAT. FF2 will snapshot on the next rising edge, at time $T_{clk}$. But a mailbox that snaps shut needs the letter already settled a little early. That early margin is the setup time $t_{su}$. So the true deadline is before the edge:

$t_{\text{deadline}}=\underset{\text{next edge}}{\underbrace{T_{clk}}}-\underset{\begin{array}{c}\text{must be stable}\\ \text{this much earlier}\end{array}}{\underbrace{t_{su}}}$

WHY $t_{su}$ exists. Inside FF2 the incoming value must charge internal nodes to a definite $0$ or $1$ before the edge locks it in. If it is still wiggling at the edge, FF2 can go metastable — stuck halfway (see Metastability). To forbid that, we insist on the margin $t_{su}$.

PICTURE. A "no-fly zone" of width $t_{su}$ is painted just before the capture edge. Data must be flat inside the whole zone.

Step 4 — Win the setup race: arrive ≤ deadline

WHAT. Demand that the arrival (Step 2) is no later than the deadline (Step 3):

$\underset{\text{arrival}}{\underbrace{t_{cq}+t_{comb}}}\le \underset{\text{deadline}}{\underbrace{T_{clk}-t_{su}}}$

Move $t_{su}$ left to collect all the "costs" on one side:

WHY the longest path. If even the slowest path fits, all faster ones fit too. So setup uses $t_{comb,max}$ — the critical path (see Critical path and pipelining). Inverting the tight case gives the top speed:

$f_{max}=\frac{1}{t_{cq}+t_{comb,max}+t_{su}}$

PICTURE. A budget bar of total length $T_{clk}$; the three coloured chunks must not overflow it.

Step 5 — The other fear: data arriving too EARLY (hold)

Now switch fears entirely.

WHAT. Look at the same edge (time $0$) at FF2. FF2 is trying to capture the old value that was already sitting on its input. But the launch edge also fired FF1, sending a new value racing down the logic. If that new value is too quick, it reaches FF2 and overwrites the input while FF2 is still capturing the old one. Corruption.

WHY use the shortest path. The danger is the fastest possible new signal, so here we use $t_{comb,min}$. The earliest the disturbance can arrive:

$t_{\text{arrive}}=\underset{\text{FF1 reacts}}{\underbrace{t_{cq}}}+\underset{\begin{array}{c}\text{fastest route}\\ \text{through logic}\end{array}}{\underbrace{t_{comb,min}}}$

PICTURE. Two edges drawn from the same clock tick. The "old" data must stay put; the "new" data must not sneak in before FF2 is done.

Step 6 — Win the hold race: don't arrive before $t_h$

WHAT. FF2 needs the old value held steady for a margin hold time $t_h$ after the edge. So the new value must not arrive until at least $t_h$ has passed:

$\underset{\text{earliest new value}}{\underbrace{t_{cq}+t_{comb,min}}}\ge \underset{\begin{array}{c}\text{keep old value}\\ \text{this long after edge}\end{array}}{\underbrace{t_h}}$

WHY this is a huge deal. Slowing the clock (bigger $T_{clk}$) helps setup — Step 4 has $T_{clk}$ on the right. But it does nothing for hold — Step 6 has no $T_{clk}$. To fix a hold violation you must add delay to the short path (insert buffers), making the new value slower. See Setup and hold time.

PICTURE. A "keep-out after the edge" zone of width $t_h$; the new-data arrow must land to the right of it.

Step 7 — Edge case: clock skew shifts the whole board

WHAT. Until now both flops saw the edge at the same instant. In reality the clock reaches FF2 slightly earlier or later than FF1. That difference is clock skew $t_{skew}=t_{capture}-t_{launch}$ (see Clock skew and clock trees).

• If $t_{skew}>0$ the capture edge arrives later → FF2's deadline moves right → more setup room.
• But that same lateness widens the same-edge hold window → less hold room.

The constraints simply pick up $t_{skew}$:

$\text{Setup: }{t}_{cq}+t_{comb,max}+t_{su}\le T_{clk}+t_{skew}$ $\text{Hold: }{t}_{cq}+t_{comb,min}\ge t_h+t_{skew}$

WHY the opposite signs. Delaying the catcher's edge relaxes "arrive early enough" (setup) but tightens "don't arrive too early" (hold). One knob, two opposite effects.

Degenerate check. Set $t_{skew}=0$ and both equations collapse back to Steps 4 and 6 — good, the general form contains the simple one.

Step 8 — Reading pass/fail: slack

WHAT. Slack = (required time) − (arrival time). Positive = pass, negative = violation.

• Setup slack $=T_{clk}-(t_{cq}+t_{comb,max}+t_{su})$
• Hold slack $=(t_{cq}+t_{comb,min})-t_h$

WHY. Slack turns an inequality into a single signed number a tool can print. It measures how much room you have (or by how much you failed).

The one-picture summary

One clock period, one launch edge, one capture edge:

• The green journey ($t_{cq}+t_{comb,max}$) must finish before the setup no-fly zone ⇒ setup uses the slow path and cares about $T_{clk}$.
• The orange journey ($t_{cq}+t_{comb,min}$) must not finish before the hold keep-out zone ⇒ hold uses the fast path and ignores $T_{clk}$.

Connections

• HDL & Digital Design Flow
• Flip-flops and sequential logic
• Setup and hold time
• Clock skew and clock trees
• Metastability
• Critical path and pipelining