Timing analysis basics (static timing) — Hinglish notes

3.5.9 · Hardware › HDL & Digital Design Flow

WHAT is STA?

Simulate kyun nahi karte? Simulation sirf unhi paths ko check karta hai jo chosen test vectors exercise karte hain. STA sab paths ko structurally check karta hai, isliye yeh timing closure guarantee kar sakta hai. Yahi 80/20 win hai: ek static analysis astronomically saari input-vector simulations ki jagah le leta hai.

The building blocks

Figure — Timing analysis basics (static timing)

HOW: setup constraint ko scratch se derive karna

Derivation. Do flip-flops consider karo FF1 (launch) → combinational logic → FF2 (capture), same clock.

Step 1 — Data FF1 se kab nikalta hai? Launch edge par (time $0$ ), plus flop ki apni delay: $t_{l a u n c h_d a t a} = t_{c q}$ Yeh step kyun? Q instantly change nahi ho sakta; yeh edge ke $t_{c q}$ baad change hota hai.

Step 2 — Data FF2 ke input par kab pahunchta hai? Logic delay add karo: $t_{a r r i v e} = t_{c q} + t_{co mb}$ Kyun? Signal ko physically gates se propagate karna padta hai.

Step 3 — FF2 par deadline. Agla capture edge $T_{c l k}$ par hai. Data $t_{s u}$ pehle stable hona chahiye: $t_{d e a d l in e} = T_{c l k} - t_{s u}$ Kyun? Setup early arrival demand karta hai.

Step 4 — Require karo arrive ≤ deadline: $t_{c q} + t_{co mb} \leq T_{c l k} - t_{s u}$

Sabse slow (longest-delay) path max frequency set karta hai → yahi critical path hai. Setup $t_{co mb, ma x}$ use karta hai.

HOW: hold constraint ko scratch se derive karna

Derivation. Dono flops usi edge ko dekhte hain (hold analysis ke liye time $0$ par).

Step 1 — Nayi data FF2 tak sabse pehle kab pahunchti hai: $t_{a r r i v e} = t_{c q} + t_{co mb, min}$ $min$ kyun? Hum yahan fastest path se darte hain — sabse jaldi possible disturbance.

Step 2 — FF2 ko purani data edge ke baad $t_{h}$ tak hold chahiye: $t_{a r r i v e} \geq t_{h}$

Slack: pass/fail number

Worked examples

Common mistakes

Active recall

Recall STA "static" kyun hai?

Kyunki yeh circuit structure se worst-case path delays analyze karta hai bina input vectors ya logic simulation ki zaroorat ke.

Recall Setup aur hold kaun si delay use karte hain?

Setup → maximum (longest) path delay. Hold → minimum (shortest) path delay.

Recall Kya clock slow karne se hold violation fix hoti hai?

Nahi. Hold $T_{c l k}$ se independent hai; tumhe data-path delay add karni hogi.

Recall Feynman: ek 12-saal ke bacche ko explain karo

Socho class mein do desks ke beech note pass karna, aur har "click" par jo teacher karta hai, note agile desk par ready hona chahiye. Setup: note ko click se thoda pehle pahunchna chahiye, warna dost use time par padh nahi sakta. Hold: note itni jaldi nahi jaana chahiye ki usi click ke dauran land kar le aur jo note abhi padha ja raha hai use kharab kar de. Agar notes bahut slow hain → clicks ke beech zyada wait karo (slower clock). Agar bahut fast hain → unhe scenic route se bhejo.

Forecast-then-Verify

Example 2 padhne se pehle, predict karo: kya 200-MHz-capable circuit 250 MHz par pass karega? (Nahi — negative slack.) Example 4 se pehle, skew ka effect predict karo. Formulas se confirm karo.

Connections

STA ka full form kya hai aur yeh kya check karta hai?

Static Timing Analysis; simulation ke bina setup/hold constraints ke against sab register-to-register paths check karta hai.

Setup constraint inequality

t_{c q} + t_{co mb, ma x} + t_{s u} \leq T_{c l k}

t_{s k e w}

agar ho toh).

Hold constraint inequality

t_{c q} + t_{co mb, min} \geq t_{h}

t_{s k e w}

agar ho toh).

Max clock frequency ka formula

f_{ma x} = 1/ (t_{c q} + t_{co mb, ma x} + t_{s u})

Setup kaun si path delay use karta hai?

Maximum (longest / critical) path.

Hold kaun si path delay use karta hai?

Minimum (shortest) path.

Kya clock period hold equation mein aata hai?

Nahi — hold

T_{c l k}

-independent hai.

Setup slack ki definition

T_{c l k} - (t_{c q} + t_{co mb} + t_{s u})

; positive = pass.

Hold violation fix kaise karte hain?

Short data path mein delay (buffers) add karo, clock slow karke nahi.

Positive clock skew (

t_{c a pt u r e}

baad mein) ka effect?

Setup relax hota hai, hold tight ho jaata hai.

STA simulation se timing ke liye behtar kyun hai?

Yeh structurally sab paths pe exhaustive hai; simulation sirf exercised vectors cover karta hai.

Setup/hold violate hone par metastability kyun hoti hai?

Flip-flop unstable data sample karta hai aur 0 aur 1 ke beech hover kar sakta hai.