4.2.13
Socho tumne ek lakhon tiny gears (transistors) wali ek badi sealed machine banayi. Manufacturing ke baad, kuch gears toot sakti hain. Lekin tum machine ko sirf bahari pins se touch kar sakte ho. Tum kaise prove karoge ki har internal gear kaam kar raha hai? DFT ek aisi art hai jisme chip mein extra "access hatches" add kiye jaate hain taaki hidden internal faults controllable (tum unhe set kar sako) aur observable (tum unhe read kar sako) ban jaayein.
Design for Testability (DFT) design techniques ka ek set hai jo ek circuit mein controllability aur observability add karta hai, taaki manufacturing defects ko fabrication ke baad efficiently detect kiya ja sake.
Controllability = primary inputs se kisi bhi internal node ko desired logic value par set karne ki ability.Observability = kisi internal node ki value ko ek primary output tak propagate karne ki ability jahan use measure kiya ja sake.
WHY it matters: Ek modern chip mein lakhon flip-flops andar gehre chhuppe hote hain. DFT ke bina, primary I/O ke zariye unhe test karna ek combinatorial nightmare hai — tumhe astronomically bahut saare test vectors ki zaroorat padegi. DFT test generation ko tractable banata hai aur fault coverage ko 99%+ ki taraf le jaata hai.
Hum har physical defect ko model nahi karte (woh infinite hain). Iske bajaye hum ek simple proxy use karte hain: stuck-at fault model. Koi node ya toh stuck-at-0 (SA0) hota hai ya stuck-at-1 (SA1) , matlab woh permanently us value se chipka hua hai chahe use koi bhi drive kare.
n 2 n single stuck-at faults ho sakte hain (har line SA0 ya SA1).
Fault coverage = total testable faults faults detected by test set
HOW you detect a stuck-at fault — tumhe ek aisa vector chahiye jo DO cheezein kare:
Activate karo fault ko: node ko stuck value ke opposite par drive karo (SA0 → use 1 par drive karo).Sensitize a path primary output tak taaki difference dikhe (observability).
Combinational logic aasaan hai — inputs directly sab kuch control karte hain. Lekin flip-flops state chhupaate hain . Kisi flip-flop ko feed karne wale logic ko test karne ke liye, tumhe pehle kaafi saare clock cycles ke zariye flip-flop ko load karna hoga, phir aur cycles ke zariye use read out karna hoga. Test complexity explode ho jaati hai. DFT ka killer app flip-flops ko directly accessible banana hai.
Scan design ordinary flip-flops ko scan flip-flops (ek MUX + FF) mein convert karta hai jo test mode mein ek shift register ki chain mein jod diye jaate hain. Isse hum saari FFs mein koi bhi state serially load kar sakte hain aur resulting state ko serially read out kar sakte hain.
Saare flip-flops ko ek dhaage par piroye huye motiyon ki tarah samjho. Scan mode mein (SE=1) tum naye motiye dhaage mein daalte ho ek per clock; normal mode mein (SE=0) woh real circuit ki tarah behave karte hain. Toh ek mushkil sequential problem ek series of combinational tests ban jaata hai.
HOW a scan test runs (one pattern):
Set karo SE=1 (shift mode). Desired FF state ko Scan-In ke zariye shift in karo — N N
Set karo SE=0 (functional mode). Primary inputs apply karo, clock ko ek baar pulse karo → combinational logic naye FF values compute karta hai (capture ).
SE=1 phir se set karo. Captured values ko Scan-Out ke zariye shift out karo (expected se compare karo) — saath hi saath agla pattern shift in karo.
N = 1000 P = 500 T ≈ ( 500 + 1 ) ( 1000 + 1 ) = 501 × 1001 ≈ 5.01 × 1 0 5 Why this step? Patterns ko per-pattern shift length se multiply karo; yahi wajah hai ki designers ek lambi chain ko bahut saari parallel scan chains mein todh dete hain — k N k
Ek mehengi bahari tester se vectors feed karne ki jagah, chip par hi ek vector generator aur ek checker rakh do . Chip khud apna test kare.
BIST ek on-chip LFSR (Linear Feedback Shift Register) ko pseudo-random pattern generator (PRPG) ke roop mein use karta hai aur ek MISR (Multiple-Input Signature Register) se saare output responses ko compress karke ek chota sa signature banata hai. Galat signature ⇒ faulty chip.
MISR mein Aliasing : ek faulty response accidentally correct signature mein compress ho jaata hai. Probability ≈ 2 − m m Why 2 − m Achhi randomness ke saath, ek galat response 2 m
Ek board par, chips solder ki gayi hoti hain — tum har solder joint ko probe nahi kar sakte. Boundary scan har chip ki pins ke around shift-register "collar" cells add karta hai taaki tum chips ke beech ki wires ko ek 4-wire interface (TDI, TDO, TCK, TMS) ke zariye test kar sako .
Boundary scan har I/O pin par ek boundary-scan cell rakhta hai, jo ek 16-state FSM se control hone wale TAP (Test Access Port) ke zariye chain kiya jaata hai. Yeh PCB par interconnect (open/short) faults test karta hai.
"Har stuck-at fault ke liye ek test vector chahiye, isliye coverage ke liye 2 n
Why it feels right: 2 n Fix: ek single vector bahut saare faults ek saath detect karta hai (fault dropping). Achha ATPG 2 n
"Scan circuit ko faster / free bana deta hai."
Why it feels right: scan "sirf ek MUX" hai. Fix: MUX functional path mein delay add karta hai aur area (~5–20% overhead) bhi, aur scan chains routing badhata hai. DFT testability ke liye performance/area trade karta hai — yeh ek deliberate cost hai.
"LFSR truly random patterns deta hai."
Why it feels right: output random lagta hai. Fix: yeh deterministic pseudo-random hai — repeatable aur periodic (period 2 n − 1
"Boundary scan chip ke andar ki logic test karta hai."
Why it feels right: yeh ek scan chain hai, internal scan ki tarah. Fix: boundary scan chips ke beech board-level interconnect target karta hai; internal scan internal logic target karta hai. Alag-alag scopes hain.
Recall Click to reveal the kid versionTumne andar lakhon tiny switches wala ek giant robot banaya, lekin use bahar sirf kuch buttons aur lights ke saath seal kar diya. Kuch switches toot sakti hain. DFT ek secret zipper add karne jaisa hai robot ki peeth par: tum unzip karte ho, ek note daakhil karte ho jo har switch ko batata hai kya banna hai, zip karte ho, "GO" ek baar press karte ho, phir unzip karke padhte ho ki har switch kya ban gaya . Agar jawab galat hai, toh koi switch toot gayi hai! Zipper hi scan chain hai, aur robot ko khud quiz karna BIST hai.
"SCAN Boundaries Bring Order to Chaos" →
S can (internal logic) · B IST (self-test on-chip) · B oundary scan (board wires) — yeh teen pillars hain.
Aur do goals ke liye: "CO" = C ontrollability + O bservability (tumhe use set bhi karna chahiye aur dekh bhi paana chahiye).
DFT ek circuit mein kaun si do properties add karta hai? Controllability (internal nodes set karna) aur Observability (internal nodes ko outputs par read karna).
Single stuck-at model mein, n lines ke liye kitne faults hote hain? 2n (har line SA0 ya SA1).
Stuck-at fault detect karne ke liye do steps kaunse hain? Activate (node ko stuck value ke opposite par drive karo) aur sensitize/propagate karo ek path ko primary output tak.
Ek ordinary flip-flop ko scan flip-flop mein kaun convert karta hai? Ek MUX add karna taaki woh functional data (D) aur scan-in ke beech shift mode (SE) mein select kare.
Scan design mein SE=1 vs SE=0 kya karta hai? SE=1 = shift mode (chain ek shift register ki tarah kaam karta hai); SE=0 = functional/capture mode.
N length ki scan chain mein P patterns ke liye approx clock cycles kitne? Lagbhag (P+1)(N+1).
Ek scan chain ko k parallel chains mein todne ki wajah kya hai? Effective chain length aur shift time ~k times kam ho jaata hai.
BIST mein patterns kaun generate karta hai aur responses kaun compress karta hai? LFSR/PRPG pseudo-random patterns generate karta hai; MISR responses ko ek signature mein compress karta hai.
Ek n-bit maximal (primitive-polynomial) LFSR kitne states se guzarta hai? 2^n - 1 (all-zero state excluded).
MISR mein aliasing kya hai aur uski probability kya hai? Ek faulty response ka correct signature mein compress ho jaana; probability ~ 2^(-m) m-bit signature ke liye.
Boundary scan (JTAG) kya test karta hai? Chips ke beech board-level interconnect (open/short faults), TDI/TDO/TCK/TMS aur TAP controller ke zariye.
Scan design ki typical cost kya hai? 5–20% area overhead plus functional path mein added delay aur extra routing.
Combinational Logic Testing — scan sequential test ko isme reduce karta hai.Automatic Test Pattern Generation (ATPG) — woh vectors generate karta hai jo scan shift in karta hai.Linear Feedback Shift Registers (LFSR) — BIST pattern generation ka engine.Flip-Flops and Sequential Circuits — scan kise modify karta hai.JTAG / IEEE 1149.1 — boundary scan standard.Yield and Fault Coverage — DFT ka economic driver.
Sequential circuits hide state
Scan flip-flops MUX plus FF
Serial shift register chain
Activate node to opposite value
