JFET structure and operation

WHAT is a JFET?

For an n-channel JFET: a bar of n-type silicon forms the channel; two p-type regions on either side form the gate. For a p-channel JFET, invert all types and voltage polarities.

WHY reverse-bias the gate? (the core trick)

HOW it operates — three regimes

Let $V_{GS}$ = gate-to-source voltage, $V_{DS}$ = drain-to-source voltage. For an n-channel device, $V_{GS} \le 0$ (gate kept negative to reverse-bias the junction).

1. Ohmic (triode) region — small $V_{DS}$

When $V_{DS}$ is tiny, the channel behaves like a plain voltage-controlled resistor. $I_D$ rises almost linearly with $V_{DS}$, and its slope is set by $V_{GS}$.

2. Pinch-off and saturation

As $V_{DS}$ increases, the depletion region near the drain grows (there the reverse bias across the junction is largest, because the channel is at a higher potential near the drain). Eventually the channel is pinched off near the drain. Beyond this, $I_D$ becomes almost constant — the device saturates.

3. Cutoff

When $V_{GS} \le V_{GS(off)}$, the depletion regions meet all along the channel: it is fully closed, $I_D \approx 0$.

DERIVATION — where the transfer equation comes from

We won't solve the full 2-D Poisson equation, but we can build Shockley's equation from physical constraints.

Step 1 — what controls $I_D$? The channel conductance depends on the open channel width. Define a normalized "how-far-from-cutoff" variable: $x = \frac{V_{GS} - V_{GS(off)}}{0 - V_{GS(off)}} = 1 - \frac{V_{GS}}{V_{GS(off)}}$ Why this step? At $V_{GS}=0$, $x=1$ (fully open). At $V_{GS}=V_{GS(off)}$, $x=0$ (fully closed). So $x$ ranges $0\to1$ and captures the fraction of "openness."

Step 2 — the width shrinks with the square root of voltage. A key result for a step junction is that the depletion width grows as $\sqrt{V}$. Working through the channel-charge integral (Shockley's analysis) gives, in saturation, that $I_D$ depends on the square of the openness variable: $\boxed{I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_{GS(off)}}\right)^2}$

Why this step? Squaring $x$ comes from integrating the channel charge along its length while the depletion width varies as $\sqrt{V}$; the algebra collapses to a clean parabola.

Step 3 — fixing the constant $I_{DSS}$. Set $V_{GS}=0$: then the bracket $=1$, so $I_D = I_{DSS}$.

Transconductance (how strongly $V_{GS}$ steers $I_D$) is the derivative: $g_m = \frac{dI_D}{dV_{GS}} = \frac{-2I_{DSS}}{V_{GS(off)}}\left(1 - \frac{V_{GS}}{V_{GS(off)}}\right) = g_{m0}\left(1-\frac{V_{GS}}{V_{GS(off)}}\right)$ where $g_{m0} = \dfrac{-2I_{DSS}}{V_{GS(off)}}$ is the transconductance at $V_{GS}=0$.

Why derive $g_m$? It's literally the slope of the transfer curve — the "gain knob" of the JFET. Steel-man: memorizing $g_m$ feels safe, but if you can differentiate Shockley you never need to memorize it.

Worked Examples

Common Mistakes (Steel-manned)

Active Recall

Connections

• BJT vs FET comparison — current-controlled vs voltage-controlled.
• MOSFET structure and operation — insulated gate replaces the PN junction.
• PN junction depletion region — the physics that forms the "valve".
• JFET biasing (self-bias, voltage-divider) — setting the operating point.
• Transconductance and small-signal models — using $g_m$ for amplifiers.
• JFET as amplifier and switch — applications of the regions above.

Concept Map

Hinglish (regional understanding)